fifo_top.vhd

设计实现4bit FIFO, 数据深度为8

Library IEEE;
Use IEEE. std_logic_1164.all;
Use IEEE. std_logic_unsigned.all;

Entity FIFO_top is
          generic (N:integer:=3;  -- width of address
                   M: integer:=4); --width of data
           port(Clk, Push, Pop, Init : in std_logic;
                  Din : in std_logic_vector(M-1 downto 0);
                  Dout :  out std_logic_vector (M-1 downto 0);
                  see_ram: out std_logic_vector(M-1 downto 0);
                  Full, Empty, Nopush, Nopop: buffer std_logic);
end entity FIFO_top;

Architecture Top_level  of FIFO_top is

Signal Address: std_logic_vector(N-1 downto 0);
Signal We : std_logic;
--signal see_ram: std_logic_vector(M-1 downto 0);

Component FIFO_control is 
  generic (N: integer);
  port( Push, Pop, Init, Clk: in std_logic;
        WE: out std_logic;
        Addr: out std_logic_vector(N-1 downto 0);
        Full, Empty, Nopop, Nopush : buffer std_logic);
end component FIFO_control;

Component RAM is
 generic(ADDRESS_WIDTH, DATA_WIDTH: integer);
 port(  clk: in std_logic;
        We : in std_logic;
        address : in std_logic_vector (ADDRESS_WIDTH-1 downto 0);
        data_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
        data_out: out std_logic_vector(DATA_WIDTH-1 downto 0);
        see_ram: out std_logic_vector(DATA_WIDTH-1 downto 0));
end component RAM;

begin
FL: FIFO_control generic map(N)
      port map(Push, Pop, Init,Clk, We, Address,Full, Empty, Nopop, Nopush);
Rmap: RAM generic map(N, M)
      port map(Clk, We, Address, Din, Dout, see_ram);
end architecture Top_level;