tb_fifo.vhd

设计实现4bit FIFO, 数据深度为8

Library IEEE;
Use IEEE. Std_logic_1164.all;
Use IEEE. std_logic_unsigned.all;
Use IEEE. std_logic_arith.all;

entity tb_fifo is 
generic (N: integer:=3;
           M: integer:=4);
end tb_fifo;

Architecture tb_tb of tb_fifo is

Component FIFO is 
  generic (N: integer;
           M: integer);
  port(Clk, Push, Pop, Init: in std_logic;
       Din: in std_logic_vector(M-1 downto 0);
       Dout: out std_logic_vector(M-1 downto 0);
       Full, Empty, Nopush, Nopop : buffer std_logic);
end component FIFO;

constant period: time:=20 ns;

signal clk_in : std_logic:='0';
signal push_in, pop_in, init_in: std_logic;
signal data_in, data_out: std_logic_vector(M-1 downto 0);
signal full_out, empty_out, nopop_out, nopush_out: std_logic;

begin

FIFOmap: FIFO generic map(N, M)
      port map(clk_in, push_in, pop_in, init_in, data_in,data_out,full_out,empty_out,       nopop_out, nopush_out);

init_in <= '1',
           '0'  after 10 ns;

generate_clk:process (clk_in)
begin
     clk_in<= not clk_in after period/2; 
end process generate_clk;

gene_push_pop: process  is
begin
    push_in <='0';
    pop_in <='0';
    wait for period;
    push_in <='1';
    pop_in <='0';
    wait for 9*period;
    push_in <='0';
    pop_in <= '1';
    wait for 9*period;
end process gene_push_pop;

gene_data : process is
begin
    data_in <="0010";
    wait for 1.5*period;
    data_in <="0000";
    wait for period;
    data_in <="0011";
    wait for period;
    data_in <="1010";
    wait for period;
    data_in <="0100";
    wait for period;
    data_in <="1000";
    wait for period;
    data_in <="0010";
    wait for period;
    data_in <="0110";
    wait for 4*period;
    data_in<="1011";
    wait for period;
    data_in<="1100";
    wait for period;
    data_in<="0111";    
end process gene_data;

end architecture tb_tb;