fifo_control.vhd

设计实现4bit FIFO, 数据深度为8

Library IEEE;
Use IEEE.std_logic_1164.all;
Use IEEE.std_logic_unsigned.all;
Use IEEE.std_logic_arith.all;

Entity FIFO_control is
         generic (N:integer:=3);
         port( Push, Pop, Init, Clk: in std_logic;
                WE: out std_logic;
                Addr: out std_logic_vector(N-1 downto 0);
                Full, Empty, Nopop, Nopush: buffer std_logic);
end entity FIFO_control;

Architecture Behavior of FIFO_control is

constant max_addr:std_logic_vector(N-1 downto 0) := (others=>'1');
constant min_addr:std_logic_vector(N-1 downto 0) := (others=>'0');
Type state_type is (A, B, C, D);   --A: empty, B:write fifo, C: full, D: read fifo
Signal current_state, next_state: state_type;
Signal counter: std_logic_vector(N downto 0);
Signal Wptr: std_logic_vector (N-1 downto 0);
Signal Rptr: std_logic_vector (N-1 downto 0);

begin

state_reg: process(Clk, Init)
begin
    if(Clk'event and Clk='1') then
         if (Init='1') then
            current_state<=A;
            Wptr <=(others =>'0');
            Rptr <=(others =>'0');
            counter <=(others=>'0');
            Addr <= (others =>'0');
          else
            current_state <= next_state;
          if (Push='1' and Pop='0' and Full='0') then
              Addr <= Wptr;
              Wptr<=Wptr+1;
              counter<=counter+1;
          elsif (Pop='1'and Push='0' and Empty='0') then
              Addr<=Rptr;
              Rptr<=Rptr+1;
              counter<=counter-1;
          elsif (Pop='1' and Push='1' and Empty='0') then
              Addr<=Rptr;
              Rptr<=Rptr+1;
              counter<=counter-1;
          end if;
          end if; 
     end if;
end process state_reg;

fsm_logic:process(current_state, Push, Pop, Full, Empty)
   begin
             case current_state is
                when A => 
                         if (Push = '1' and Pop='0' ) then
                            next_state <= B;
                            We <= '1';
                            --Addr <= Wptr;
                         else
                            next_state <= A;
                         end if;
                when B =>
                         if (Push='1' and Pop = '0' ) then
                              if (Full='0') then
                                 next_state <= B;
                                 --Addr <= Wptr;
                                 We <= '1';
                               else
                                  next_state <=C;
                                  --We <='0';
                               end if;
                        elsif (Push = '0' and Pop = '1') or  (Push = '1' and Pop ='1') then
                               if (Empty='0') then
                                  next_state <= D;
                                  --Addr <= Rptr;
                                  We <= '0';
                                end if;
                        elsif (Push='0' and Pop='0') then
                                next_state<= B;
                        end if;
               when C => 
                            if (Push='1' and Pop='0') then
                               next_state <= C;
                               --We <= '0';
                            elsif (Pop='0' and Push='0') then
                              next_state <=C;
                               --We <='0';
                            else
                                 next_state <= D;
                                 We<='0';
                                 --Addr <= Rptr;
                            end if;
              when D =>
                         if (Push='1' and Pop='0') then
                              next_state<=B;
                              --Addr <= Wptr;
                              We <= '1';
                         elsif (Push='0' and Pop='1') or (Push='1' and Pop='1') then
                            if (empty='0') then
                               next_state<=D;
                               --Addr<= Rptr;
                               We <= '0';
                             else
                                next_state <= A;
                             end if;
                         elsif  (Push='0' and Pop='0') then
                               next_state <=D;
                        end if;
             end case;                   
end process fsm_logic;

indicator1: process (counter)
begin
     --if (Clk'event and Clk='1') then
      if (counter(N) = '1')then
           Full <= '1';
      else
           Full <='0';
      end if;

      if (counter = ('0'& min_addr)) then
          Empty <= '1';
      else
          Empty <= '0';
      end if;
     --end if;
end process indicator1;

indicator2: process(Push, Pop, Full, Empty)
begin
     if (Push='1' and Pop='1') then
         Nopush<='1';
         Nopop<='0';
     elsif (Full='1' and Push='1') then
         Nopush<='1';
         Nopop<='0';
     elsif (Empty='1' and Pop='1') then
         Nopush<='0';
         Nopop<='1';
     else
         Nopush<='0';
         Nopop<='0';
     end if; 
end process indicator2;

end architecture Behavior;