ram_beh.vhd

设计实现4bit FIFO, 数据深度为8

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity RAM is
    generic(
        ADDRESS_WIDTH : integer;
        DATA_WIDTH : integer
        );
    port(
        clk : in std_logic;
        we : in std_logic;
        address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
        data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
        data_out : out std_logic_vector(DATA_WIDTH-1 downto 0);
        see_ram: out std_logic_vector(DATA_WIDTH-1 downto 0)
        );
end entity RAM;

architecture behavioral of RAM is
    type RAM_type is array(0 to (2**address'length)-1) of std_logic_vector(data_in'range);
    signal RAM_DATA : RAM_type;
    signal sampled_address : std_logic_vector(address'range);
begin
    process(clk) is
    begin
    
    if (rising_edge(clk)) then
       if(we = '1') then
           RAM_DATA(to_integer(unsigned(address))) <= data_in;
       else
        data_out<=RAM_DATA(to_integer(unsigned(sampled_address)));
       end if;
       sampled_address <= address;
    end if;
    
end process;
--data_out<= RAM_DATA(to_integer(unsigned(sampled_address)));
see_ram <= RAM_DATA(to_integer(unsigned(sampled_address)));
end architecture behavioral;