📄 sacmv32.lst
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< .DEFINE C_Manual_Mode 0x0000; //b4=0: A/D manual mode
< //b5: ADINI?
< .DEFINE C_DAC_Current_2mA 0x0040; //b6=1: DAC current = 2mA @ vdd=3V(new option)
< .DEFINE C_DAC_Current_3mA 0x0000; //b6=0: DAC current = 3mA @ vdd=3V(Default)
< .DEFINE C_AD_Vref_VDD 0x0080; //b7=1: Vref is VDD
< .DEFINE C_AD_Vref_VRTPAD 0x0000; //b7=0: Vref is from pin "VRTPAD"
< .DEFINE C_AD_COMP 0x4000; //b14=1: output voltage of DAC0<Analog input signal
< //b14=0: output voltage of DAC0>Analog input signal
< .DEFINE C_AD_RDY 0x8000; //b15=1: A/D digital data ready; 0: not ready
< .endif
<
< .if BODY_TYPE == SPCE500A
< .DEFINE C_AD 0x0001 //
< .DEFINE C_DA 0x0000 //
< .DEFINE C_MIC 0x0000 //
< .DEFINE C_LINE 0x0002 //
< .endif
< //----------------------------------------------
<
<
< // Define for P_DAC_Ctrl
< //----------------------------------------------
< .if BODY_TYPE == SPCE061A
< .DEFINE C_DAC1_Direct 0x0000; // b8 b7: DAC1 latch
< .DEFINE C_DAC1_LatchA 0x0080; // Latch data to DAC1 by TimerA
< .DEFINE C_DAC1_LatchB 0x0100; // Latch data to DAC1 by TimerB
< .DEFINE C_DAC1_LatchAB 0x0180; // Latch data to DAC1 by TimerA or TimerB
<
< .DEFINE C_DAC2_Direct 0x0000; // b6 b5: DAC2 latch
< .DEFINE C_DAC2_LatchA 0x0020; // Latch data to DAC2 by TimerA
< .DEFINE C_DAC2_LatchB 0x0040; // Latch data to DAC2 by TimerB
< .DEFINE C_DAC2_LatchAB 0x0060; // Latch data to DAC2 by TimerA or TimerB
<
< .DEFINE C_ADC_Direct 0x0000; // b4 b3: ADC latch
< .DEFINE C_ADC_LatchA 0x0008; // Latch data to ADC by TimerA
< .DEFINE C_ADC_LatchB 0x0010; // Latch data to ADC by TimerB
< .DEFINE C_ADC_LatchAB 0x0018; // Latch data to ADC by TimerA or TimerB
< .endif
<
< .if BODY_TYPE == SPCE500A
< .DEFINE C_PushPull 0x0000 // b0, (default)
< .DEFINE C_DoubleEnd 0x0001 // b0
< .DEFINE C_DAC_Mode 0x0000 // b1, (default)
< .DEFINE C_PWM_Mode 0x0002 // b1
<
< .DEFINE C_D1_Direct 0x0000 // DAC1 latch
< .DEFINE C_D1_LatchA 0x0008 //
< .DEFINE C_D1_LatchB 0x0010 //
< .DEFINE C_D1_LatchAB 0x0018 //
<
< .DEFINE C_D2_Direct 0x0000 // DAC2 latch
< .DEFINE C_D2_LatchA 0x0020 //
< .DEFINE C_D2_LatchB 0x0040 //
< .DEFINE C_D2_LatchAB 0x00C0 //
< .endif
< //----------------------------------------------
<
< // Define for P_LVD_Ctrl
< //----------------------------------------------
< .if BODY_TYPE == SPCE061A
< .DEFINE C_LVD24V 0x0000; // LVD = 2.4V; b1b0
< .DEFINE C_LVD28V 0x0001; // LVD = 2.8V
< .DEFINE C_LVD32V 0x0002; // LVD = 3.2V
< .endif
<
< .if BODY_TYPE == SPCE500A
< .DEFINE C_LVD26V 0x0000 // LVD = 2.6V
< .DEFINE C_LVD30V 0x0001 // LVD = 3.0V
< .DEFINE C_LVD36V 0x0002 // LVD = 3.6V
< .DEFINE C_LVD40V 0x0003 // LVD = 4.0V
< .endif
<
< .DEFINE C_LVD_Result 0x8000; // b15 = 1: below the selected LVD level
< //----------------------------------------------
<
<
< // SPCE061 flash operation instruction definition
< //----------------------------------------------
< .if BODY_TYPE == SPCE061A
< .DEFINE C_EnableFlashAccess 0xAAAA;
< .DEFINE C_EraseFlashPage 0x5511;
< .DEFINE C_ProgramFlash 0x5533;
< .endif
< //----------------------------------------------
<
<
<
< //===============================================================
< // Sunplus APIs for SPCE 061A
< //===============================================================
< //////////////////////////////////////////////////
< // Note: This register will map to the P_INT_Ctrl
< // (0x7010), The SACMvxx.lib use this register to
< // combine with user's interrupt setting.
< // In SPCE061, it is not necessary since the
< // P_INT_Mask(0x702D) already does this. It is for
< // compatibility to keep it here.
< //////////////////////////////////////////////////
< //.EXTERNAL R_InterruptStatus
<
< //========================================================================================
< // End of SPCE.inc
< //========================================================================================
<
<
<
//== User definition =====================
.define C_RampDelay 80
//---<< System Clock Setting >>----------------------
// Note: Please refer to spce.inc for BODY_TYPE definition.
// This setting affects the validity of C_SystemClock.
//
.define C_SystemClock C_Fosc_49M
//.define C_SystemClock C_Fosc
//----<< Timer definition >>------------------------
.define C_Timer_Setting_8K_For_24MHz 0xF9FF
.define C_Timer_Setting_9K_For_24MHz 0xFAAA
.define C_Timer_Setting_10K_For_24MHz 0xFB33
.define C_Timer_Setting_11K_For_24MHz 0xFBA2
.define C_Timer_Setting_12K_For_24MHz 0xFBFF
.define C_Timer_Setting_16K_For_24MHz 0xFCFF
.define C_Timer_Setting_20K_For_24MHz 0xFD98
.define C_Timer_Setting_24K_For_24MHz 0xFDFF
.define C_Timer_Setting_8K_For_49MHz 0xF3FF
.define C_Timer_Setting_9K_For_49MHz 0xF555
.define C_Timer_Setting_10K_For_49MHz 0xF666
.define C_Timer_Setting_11K_For_49MHz 0xF745
.define C_Timer_Setting_12K_For_49MHz 0xF7FF
.define C_Timer_Setting_16K_For_49MHz 0xF9FF
.define C_Timer_Setting_20K_For_49MHz 0xFB33
.define C_Timer_Setting_24K_For_49MHz 0xFBFF
//---<< Timer setting >>
.define C_S200_Timer_Setting C_Timer_Setting_16K_For_49MHz
.define C_S240_Timer_Setting C_Timer_Setting_20K_For_49MHz
.define C_S480_Timer_Setting C_Timer_Setting_16K_For_49MHz
.define C_S530_Timer_Setting C_Timer_Setting_12K_For_49MHz
.define C_A1600_Timer_Setting C_Timer_Setting_16K_For_49MHz
.define C_A2000_Timer_Setting C_Timer_Setting_16K_For_49MHz
.define C_DVR_Timer_Setting C_Timer_Setting_8K_For_49MHz
.define C_DVR_Rec_Timer_Setting C_Timer_Setting_24K_For_49MHz
.define C_DVR_Play_Timer_Setting C_Timer_Setting_16K_For_49MHz
// For A3200 Timer setting , please go to F_SP_SACM_A3200_Init_,
// F_SP_SACM_2Ch_A3200_Init_
// it is determined by library internally.
// For Ms01 Timer setting , please go to F_SP_SACM_MS01_Init_
//-------------------------------------------------
//==================================================
.PUBLIC F_SP_RampUpDAC1
.PUBLIC F_SP_RampDnDAC1
.PUBLIC F_SP_RampUpDAC2
.PUBLIC F_SP_RampDnDAC2
.PUBLIC _SP_RampUpDAC1
.PUBLIC _SP_RampDnDAC1
.PUBLIC _SP_RampUpDAC2
.PUBLIC _SP_RampDnDAC2
.PUBLIC _SP_InitQueue
.PUBLIC _SP_InitQueue_A2000
.PUBLIC _SP_InitQueue_S530
.PUBLIC _SP_InitQueue_S480
.PUBLIC _SP_InitQueue_S240
.PUBLIC _SP_InitQueue_MS01
.PUBLIC _SP_InitQueue_DVR
.PUBLIC F_SP_InitQueue
.PUBLIC F_SP_InitQueue_A2000
.PUBLIC F_SP_InitQueue_S530
.PUBLIC F_SP_InitQueue_S480
.PUBLIC F_SP_InitQueue_S240
.PUBLIC F_SP_InitQueue_MS01
.PUBLIC F_SP_InitQueue_DVR
.PUBLIC F_SP_ReadQueue
.PUBLIC F_SP_ReadQueue_A2000
.PUBLIC F_SP_ReadQueue_S530
.PUBLIC F_SP_ReadQueue_S480
.PUBLIC F_SP_ReadQueue_S240
.PUBLIC F_SP_ReadQueue_MS01
.PUBLIC F_SP_ReadQueue_DVR
.PUBLIC F_SP_ReadQueue_NIC // Read Queue with no index change
.PUBLIC F_SP_ReadQueue_NIC_A2000
.PUBLIC F_SP_ReadQueue_NIC_S530
.PUBLIC F_SP_ReadQueue_NIC_S480
.PUBLIC F_SP_ReadQueue_NIC_S240
.PUBLIC F_SP_ReadQueue_NIC_MS01
.PUBLIC F_SP_ReadQueue_NIC_DVR
.PUBLIC F_SP_WriteQueue
.PUBLIC F_SP_WriteQueue_A2000
.PUBLIC F_SP_WriteQueue_S530
.PUBLIC F_SP_WriteQueue_S480
.PUBLIC F_SP_WriteQueue_S240
.PUBLIC F_SP_WriteQueue_MS01
.PUBLIC F_SP_WriteQueue_DVR
.PUBLIC F_SP_TestQueue
.PUBLIC F_SP_TestQueue_A2000
.PUBLIC F_SP_TestQueue_S530
.PUBLIC F_SP_TestQueue_S480
.PUBLIC F_SP_TestQueue_S240
.PUBLIC F_SP_TestQueue_MS01
.PUBLIC F_SP_TestQueue_DVR
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