📄 pci_init.h
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/* mot83xxPci.c - PPC83xx PCI Bridge functions */
/*
* Copyright (c) 2006 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use
* of this software may be licensed only pursuant to the terms
* of an applicable Wind River license agreement.
*/
/*
modification history
--------------------
01d,14mar06,kds PCI2_GCR set to 0x1 for 32b PCI operation.
01c,09aug05,j_b doc cleanup
01b,04apr05,mdo Documentation fixes for apigen
01a,04feb05,dtr File created from mot85xxPci.c.
*/
/*
DESCRIPTION
This file contains the PCI Host Bridge setup File.
INCLUDE FILES:
*/
#include <VXWORKS.H>
#include "config.h"
#include <SYSLIB.H>
#include <DRV pciConfigLib.h pci>
#include <DRV pci pciIntLib.h>
#include <DRV pci pciAutoConfigLib.h>
#include "sysBusPci.h"
#include "mot83xxPci.h"
#define MAX_NUM_VECTORS 4
UINT32 pciRegRead(UINT32 *adrs);
void pciRegWrite(UINT32 *adrs,UINT32 value);
void pciConfigTest();
#define PCI_REG_READ pciRegRead
#define PCI_REG_WRITE pciRegWrite
/*************************************************************************
*
* mot83xxBridgeInit - initialize the PCI Bridge
*
* This function performs all the initialization required for the
* Bridge/Interrupts/PCI Bus to function. It does some low level processor
* initialization which might normally be done in romInit as it is optional
* to do use this and shows what the core changes required to bring up the
* bridge.
*
* RETURNS: N/A
*
* ERRNO
*/
void mot83xxBridgeInit (void)
{
STATUS result;
/* Initialize LAWBAR/LAWAR for PCI */
*PCI1_GCR(CCSBAR) = 0x1; /* Clear PCI reset */
/* Allow time for PCI bus to come out of reset */
{
volatile int i ;
for (i = 0 ; i < 0x80000 ; i++) ;
WRS_ASM("isync");
}
*PCI1_GCR(CCSBAR) = 0x0; /* Put PCI reset */
/* Allow time for PCI bus to reset */
{
volatile int i ;
for (i = 0 ; i < 0x80000 ; i++) ;
WRS_ASM("isync");
}
*PCI1_GCR(CCSBAR) = 0x1; /* Clear PCI reset */
/* Allow time for PCI Bus to come out of reset */
{
volatile int i;
for (i = 0 ; i < 0x80000 ; i++)
WRS_ASM("isync");
}
/* Initialize LAWBAR/LAWAR for PCI */
*M83XX_PCILAWBARn(CCSBAR,0) = CPU_PCI_MEM_ADRS ;
*M83XX_PCILAWARn(CCSBAR,0) = LAWAR_ENABLE | LAWAR_SIZE_256MB;
*PCI1_ECR(CCSBAR) = 0x0; /* Generate interrupt if PCI error and ESR set*/
*PCI1_ESR(CCSBAR) = 0xffffffff; /* Clear status */
*PCI1_GCR(CCSBAR) = 0x1; /* Clear PCI1 reset */
*PCI2_GCR(CCSBAR) = 0x1; /* Clear PCI2 reset */
/* May need to handle target abort */
sysPciConfigEnable(PCI_1_BUS);
/* Set outbound translation window addresses */
result = sysPciConfigWrite(0,0,0,
PCI_CFG_BASE_ADDRESS_0,
0x4,
PCI_BRIDGE_PIMMR_BASE_ADRS);
PCI_REG_WRITE((UINT32*)(PCI_OUTBOUND_BASE_ADRS_REGn(CCSBAR,0)),
CPU_PCI_MEM_ADRS >> 12);
PCI_REG_WRITE((UINT32*)(PCI_OUTBOUND_TRANS_ADRS_REGn(CCSBAR,0)),
PCI_MEM_ADRS >> 12);
PCI_REG_WRITE((UINT32*)(PCI_OUTBOUND_BASE_ADRS_REGn(CCSBAR,1)),
CPU_PCI_MEMIO_ADRS >> 12);
PCI_REG_WRITE((UINT32*)(PCI_OUTBOUND_TRANS_ADRS_REGn(CCSBAR,1)),
PCI_MEMIO_ADRS >> 12);
PCI_REG_WRITE((UINT32*)(PCI_OUTBOUND_BASE_ADRS_REGn(CCSBAR,2)),
CPU_PCI_IO_ADRS >> 12);
PCI_REG_WRITE((UINT32*)(PCI_OUTBOUND_BASE_ADRS_REGn(CCSBAR,2)),
PCI_IO_ADRS >> 12);
/* Switch on the outbound translation windows */
PCI_REG_WRITE((UINT32*)(PCI_OUTBOUND_ATTR_REGn(CCSBAR,0)),
0xa00f8000); /* Enable|128MB */
PCI_REG_WRITE((UINT32*)(PCI_OUTBOUND_ATTR_REGn(CCSBAR,1)),
0xa00fc000); /* Enable|64MB */
PCI_REG_WRITE((UINT32*)(PCI_OUTBOUND_ATTR_REGn(CCSBAR,2)),
0xc00fc000); /* Enable|64MB */
PCI_REG_WRITE((UINT32*)(PCI1_INBOUND_BASE_ADRS_REGn(CCSBAR,1)),
0);
PCI_REG_WRITE((UINT32*)(PCI1_INBOUND_TRANS_ADRS_REGn(CCSBAR,1)),
0);
PCI_REG_WRITE((UINT32*)(PCI1_INBOUND_ATTR_REGn(CCSBAR,1)),
PCI_WINDOW_ENABLE_BIT |
PCI_IN_ATTR_RTT_LM_WRITE_SNOOP |
PCI_IN_ATTR_RTT_LM_READ_SNOOP |
PCI_ATTR_WS_256M);
PCI_REG_WRITE((UINT32*)(PCI1_INBOUND_ATTR_REGn(CCSBAR,2)),
0x0);
PCI_REG_WRITE((UINT32*)(PCI1_INBOUND_ATTR_REGn(CCSBAR,3)),
0x0);
/* configure the bridge as bus master */
result = sysPciConfigWrite(0,0,0,
COMMAND_REGISTER_OFFSET,
COMMAND_REGISTER_WIDTH,
PCI_CMD_IO_ENABLE |
PCI_CMD_MEM_ENABLE |
PCI_CMD_MASTER_ENABLE);
}
void pciRegWrite
(
UINT32 *adrs,
UINT32 value
)
{
*adrs = value;
WRS_ASM("isync;sync");
}
UINT32 pciRegRead
(
UINT32 *adrs
)
{
return(*adrs);
}
void pciConfigTest (void)
{
int loop;
UINT32 var;
for (loop=0;loop<0x40;loop+=4)
{
sysPciConfigRead(0,0,0,loop,0x4,&var);
printf("Word %d Value %x\n",loop,var);
}
}
/* mot83xxPci.c - PPC83xx PCI Bridge functions */
/*
* Copyright (c) 2006 Wind River Systems, Inc.
*
* The right to copy, distribute, modify or otherwise make use
* of this software may be licensed only pursuant to the terms
* of an applicable Wind River license agreement.
*/
/*
modification history
--------------------
01d,14mar06,kds PCI2_GCR set to 0x1 for 32b PCI operation.
01c,09aug05,j_b doc cleanup
01b,04apr05,mdo Documentation fixes for apigen
01a,04feb05,dtr File created from mot85xxPci.c.
*/
/*
DESCRIPTION
This file contains the PCI Host Bridge setup File.
INCLUDE FILES:
*/
#include
#include "config.h"
#include
#include
#include
#include
#include "sysBusPci.h"
#include "mot83xxPci.h"
#define MAX_NUM_VECTORS 4
UINT32 pciRegRead(UINT32 *adrs);
void pciRegWrite(UINT32 *adrs,UINT32 value);
void pciConfigTest();
#define PCI_REG_READ pciRegRead
#define PCI_REG_WRITE pciRegWrite
/*************************************************************************
*
* mot83xxBridgeInit - initialize the PCI Bridge
*
* This function performs all the initialization required for the
* Bridge/Interrupts/PCI Bus to function. It does some low level processor
* initialization which might normally be done in romInit as it is optional
* to do use this and shows what the core changes required to bring up the
* bridge.
*
* RETURNS: N/A
*
* ERRNO
*/
void mot83xxBridgeInit (void)
{
STATUS result;
/* Initialize LAWBAR/LAWAR for PCI */
*PCI1_GCR(CCSBAR) = 0x1; /* Clear PCI reset */
/* Allow time for PCI bus to come out of reset */
{
volatile int i ;
for (i = 0 ; i < 0x80000 ; i++) ;
WRS_ASM("isync");
}
*PCI1_GCR(CCSBAR) = 0x0; /* Put PCI reset */
/* Allow time for PCI bus to reset */
{
volatile int i ;
for (i = 0 ; i < 0x80000 ; i++) ;
WRS_ASM("isync");
}
*PCI1_GCR(CCSBAR) = 0x1; /* Clear PCI reset */
/* Allow time for PCI Bus to come out of reset */
{
volatile int i;
for (i = 0 ; i < 0x80000 ; i++)
WRS_ASM("isync");
}
/* Initialize LAWBAR/LAWAR for PCI */
*M83XX_PCILAWBARn(CCSBAR,0) = CPU_PCI_MEM_ADRS ;
*M83XX_PCILAWARn(CCSBAR,0) = LAWAR_ENABLE | LAWAR_SIZE_256MB;
*PCI1_ECR(CCSBAR) = 0x0; /* Generate interrupt if PCI error and ESR set*/
*PCI1_ESR(CCSBAR) = 0xffffffff; /* Clear status */
*PCI1_GCR(CCSBAR) = 0x1; /* Clear PCI1 reset */
*PCI2_GCR(CCSBAR) = 0x1; /* Clear PCI2 reset */
/* May need to handle target abort */
sysPciConfigEnable(PCI_1_BUS);
/* Set outbound translation window addresses */
result = sysPciConfigWrite(0,0,0,
PCI_CFG_BASE_ADDRESS_0,
0x4,
PCI_BRIDGE_PIMMR_BASE_ADRS);
PCI_REG_WRITE((UINT32*)(PCI_OUTBOUND_BASE_ADRS_REGn(CCSBAR,0)),
CPU_PCI_MEM_ADRS >> 12);
PCI_REG_WRITE((UINT32*)(PCI_OUTBOUND_TRANS_ADRS_REGn(CCSBAR,0)),
PCI_MEM_ADRS >> 12);
PCI_REG_WRITE((UINT32*)(PCI_OUTBOUND_BASE_ADRS_REGn(CCSBAR,1)),
CPU_PCI_MEMIO_ADRS >> 12);
PCI_REG_WRITE((UINT32*)(PCI_OUTBOUND_TRANS_ADRS_REGn(CCSBAR,1)),
PCI_MEMIO_ADRS >> 12);
PCI_REG_WRITE((UINT32*)(PCI_OUTBOUND_BASE_ADRS_REGn(CCSBAR,2)),
CPU_PCI_IO_ADRS >> 12);
PCI_REG_WRITE((UINT32*)(PCI_OUTBOUND_BASE_ADRS_REGn(CCSBAR,2)),
PCI_IO_ADRS >> 12);
/* Switch on the outbound translation windows */
PCI_REG_WRITE((UINT32*)(PCI_OUTBOUND_ATTR_REGn(CCSBAR,0)),
0xa00f8000); /* Enable|128MB */
PCI_REG_WRITE((UINT32*)(PCI_OUTBOUND_ATTR_REGn(CCSBAR,1)),
0xa00fc000); /* Enable|64MB */
PCI_REG_WRITE((UINT32*)(PCI_OUTBOUND_ATTR_REGn(CCSBAR,2)),
0xc00fc000); /* Enable|64MB */
PCI_REG_WRITE((UINT32*)(PCI1_INBOUND_BASE_ADRS_REGn(CCSBAR,1)),
0);
PCI_REG_WRITE((UINT32*)(PCI1_INBOUND_TRANS_ADRS_REGn(CCSBAR,1)),
0);
PCI_REG_WRITE((UINT32*)(PCI1_INBOUND_ATTR_REGn(CCSBAR,1)),
PCI_WINDOW_ENABLE_BIT |
PCI_IN_ATTR_RTT_LM_WRITE_SNOOP |
PCI_IN_ATTR_RTT_LM_READ_SNOOP |
PCI_ATTR_WS_256M);
PCI_REG_WRITE((UINT32*)(PCI1_INBOUND_ATTR_REGn(CCSBAR,2)),
0x0);
PCI_REG_WRITE((UINT32*)(PCI1_INBOUND_ATTR_REGn(CCSBAR,3)),
0x0);
/* configure the bridge as bus master */
result = sysPciConfigWrite(0,0,0,
COMMAND_REGISTER_OFFSET,
COMMAND_REGISTER_WIDTH,
PCI_CMD_IO_ENABLE |
PCI_CMD_MEM_ENABLE |
PCI_CMD_MASTER_ENABLE);
}
void pciRegWrite
(
UINT32 *adrs,
UINT32 value
)
{
*adrs = value;
WRS_ASM("isync;sync");
}
UINT32 pciRegRead
(
UINT32 *adrs
)
{
return(*adrs);
}
void pciConfigTest (void)
{
int loop;
UINT32 var;
for (loop=0;loop<0x40;loop+=4)
{
sysPciConfigRead(0,0,0,loop,0x4,&var);
printf("Word %d Value %x\n",loop,var);
}
}
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