zhishu.vhd

来自「八音自动播放电子琴设计」· VHDL 代码 · 共 40 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity zhishu is 
  port(yuepu :in integer range 0 to 21;
       shu : out integer range 4641 to 16383 );
end zhishu;

architecture zhi of zhishu is
   begin 
    process (yuepu) 
      begin 
          case yuepu is 
              when 0 =>shu<=16383;
              when 1 =>shu<=4641;
              when 2 =>shu<=5924;
              when 3 =>shu<=7064;
              when 4 =>shu<=7587;
              when 5 =>shu<=8547;
              when 6 =>shu<=9402;
              when 7 =>shu<=10164;
              when 8 =>shu<=10514;
              when 9 =>shu<=11154;
              when 10 =>shu<=11724;
              when 11 =>shu<=11986;
              when 12 =>shu<=12466;
              when 13 =>shu<=12893;
              when 14 =>shu<=13274;
              when 15 =>shu<=13449;
              when 16 =>shu<=13769;
              when 17 =>shu<=14054;
              when 18 =>shu<=14185;
              when 19 =>shu<=14425;
              when 20 =>shu<=14639;
              when 21 =>shu<=14829;
              when others => shu <=16383;
           end case;
    end process;
end zhi;