key_xuange.vhd

来自「八音自动播放电子琴设计」· VHDL 代码 · 共 25 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity key_xuange is
      port( key :in std_logic;  
           enable:out std_logic);
end key_xuange;
 
architecture xuange of key_xuange is
   signal count1 :integer range 0 to 1;
 begin 
   process(key)
   begin  
     if (key'event and key='1')then
        if (count1=1) then 
            count1<=0;enable<='1';
        else
           count1<=count1+1; enable<='0';
        end if;
     end if;
   end process;
 end xuange;