📄 zhilv.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity zhilv is
port(clk : in std_logic;
shu : in integer range 4641 to 16383 ;
sound : out std_logic);
end zhilv ;
architecture pin of zhilv is
signal clks : std_logic;
signal sounds,soundsss3 : std_logic;
--signal count4 : std_logic;
begin
process(clk)
variable countss3: integer range 0 to 3;
begin
if(clk'event and clk='1') then
if(countss3=3)then
countss3 :=0 ; soundsss3 <='1';
else
countss3 :=countss3 + 1;
soundsss3 <='0';
end if;
end if;
end process;
process(soundsss3)
variable count3: integer range 4641 to 16383;
begin
if(soundsss3'event and soundsss3='1') then
if(count3 = 16383) then
count3 :=shu ; sounds <='1';
else
count3 :=count3 + 1;
sounds <='0';
end if;
end if;
end process;
process(sounds)
variable count4 : std_logic;
begin
if(sounds'event and sounds='1') then
count4 := not count4;
if(count4='1')then
sound<='1';
else
sound<='0';
end if ;
end if ;
end process;
-- process(sounds)
-- begin
-- if(sounds'event and sounds='1') then
-- count4 <= not count4;
-- end if ;
-- end process;
-- process(key)
-- begin
-- if(key'event and key='1') then
-- if(count4='1')then
-- sound<='1';
-- else
-- sound<='0';
-- end if ;
-- end if ;
-- end process;
end pin;
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