📄 music.map.rpt
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; Source assignments for key_xuange:inst14 ;
+----------------+-------+------+----------+
; Assignment ; Value ; From ; To ;
+----------------+-------+------+----------+
; POWER_UP_LEVEL ; Low ; - ; count1 ;
+----------------+-------+------+----------+
+--------------------------------------------+
; Source assignments for maoci:inst1 ;
+----------------+-------+------+------------+
; Assignment ; Value ; From ; To ;
+----------------+-------+------+------------+
; POWER_UP_LEVEL ; Low ; - ; count0[0] ;
; POWER_UP_LEVEL ; Low ; - ; count0[1] ;
; POWER_UP_LEVEL ; Low ; - ; count0[2] ;
; POWER_UP_LEVEL ; Low ; - ; count0[3] ;
; POWER_UP_LEVEL ; Low ; - ; count0[4] ;
; POWER_UP_LEVEL ; Low ; - ; count0[5] ;
; POWER_UP_LEVEL ; Low ; - ; count0[6] ;
; POWER_UP_LEVEL ; Low ; - ; count0[7] ;
; POWER_UP_LEVEL ; Low ; - ; count0[8] ;
; POWER_UP_LEVEL ; Low ; - ; count0[9] ;
; POWER_UP_LEVEL ; Low ; - ; count0[10] ;
; POWER_UP_LEVEL ; Low ; - ; count0[11] ;
; POWER_UP_LEVEL ; Low ; - ; count0[12] ;
; POWER_UP_LEVEL ; Low ; - ; count0[13] ;
; POWER_UP_LEVEL ; Low ; - ; count0[14] ;
; POWER_UP_LEVEL ; Low ; - ; count0[15] ;
; POWER_UP_LEVEL ; Low ; - ; count0[16] ;
; POWER_UP_LEVEL ; Low ; - ; count0[17] ;
; POWER_UP_LEVEL ; Low ; - ; count0[18] ;
; POWER_UP_LEVEL ; Low ; - ; count0[19] ;
; POWER_UP_LEVEL ; Low ; - ; count0[20] ;
; POWER_UP_LEVEL ; Low ; - ; count0[21] ;
; POWER_UP_LEVEL ; Low ; - ; count0[22] ;
; POWER_UP_LEVEL ; Low ; - ; count0[23] ;
+----------------+-------+------+------------+
+-----------------------------------------------------------------------------------------+
; Source assignments for zhiyin:inst9|altsyncram:Mux5_rtl_0|altsyncram_mau:auto_generated ;
+---------------------------------+--------------------+------+---------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+--------------------+------+---------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
+---------------------------------+--------------------+------+---------------------------+
+-------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: zhiyin:inst9|altsyncram:Mux5_rtl_0 ;
+------------------------------------+----------------+-------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------------------+----------------+-------------------------------+
; BYTE_SIZE_BLOCK ; 8 ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; OPERATION_MODE ; ROM ; Untyped ;
; WIDTH_A ; 5 ; Untyped ;
; WIDTHAD_A ; 10 ; Untyped ;
; NUMWORDS_A ; 1024 ; Untyped ;
; OUTDATA_REG_A ; UNREGISTERED ; Untyped ;
; ADDRESS_ACLR_A ; NONE ; Untyped ;
; OUTDATA_ACLR_A ; NONE ; Untyped ;
; WRCONTROL_ACLR_A ; NONE ; Untyped ;
; INDATA_ACLR_A ; NONE ; Untyped ;
; BYTEENA_ACLR_A ; NONE ; Untyped ;
; WIDTH_B ; 1 ; Untyped ;
; WIDTHAD_B ; 1 ; Untyped ;
; NUMWORDS_B ; 1 ; Untyped ;
; INDATA_REG_B ; CLOCK1 ; Untyped ;
; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ;
; RDCONTROL_REG_B ; CLOCK1 ; Untyped ;
; ADDRESS_REG_B ; CLOCK1 ; Untyped ;
; OUTDATA_REG_B ; UNREGISTERED ; Untyped ;
; BYTEENA_REG_B ; CLOCK1 ; Untyped ;
; INDATA_ACLR_B ; NONE ; Untyped ;
; WRCONTROL_ACLR_B ; NONE ; Untyped ;
; ADDRESS_ACLR_B ; NONE ; Untyped ;
; OUTDATA_ACLR_B ; NONE ; Untyped ;
; RDCONTROL_ACLR_B ; NONE ; Untyped ;
; BYTEENA_ACLR_B ; NONE ; Untyped ;
; WIDTH_BYTEENA_A ; 1 ; Untyped ;
; WIDTH_BYTEENA_B ; 1 ; Untyped ;
; RAM_BLOCK_TYPE ; AUTO ; Untyped ;
; BYTE_SIZE ; 8 ; Untyped ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ;
; INIT_FILE ; music0.rtl.mif ; Untyped ;
; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;
; MAXIMUM_DEPTH ; 0 ; Untyped ;
; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ;
; DEVICE_FAMILY ; Cyclone ; Untyped ;
; CBXI_PARAMETER ; altsyncram_mau ; Untyped ;
+------------------------------------+----------------+-------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Mon Jan 14 15:33:33 2002
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off music -c music
Info: Found 1 design units, including 1 entities, in source file music.bdf
Info: Found entity 1: music
Info: Elaborating entity "music" for the top level hierarchy
Warning: Using design file zhilv.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: zhilv-pin
Info: Found entity 1: zhilv
Info: Elaborating entity "zhilv" for hierarchy "zhilv:inst"
Warning: Using design file zhishu.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: zhishu-zhi
Info: Found entity 1: zhishu
Info: Elaborating entity "zhishu" for hierarchy "zhishu:inst12"
Warning: Using design file zhiyin.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: zhiyin-zhi
Info: Found entity 1: zhiyin
Info: Elaborating entity "zhiyin" for hierarchy "zhiyin:inst9"
Warning (10492): VHDL Process Statement warning at zhiyin.vhd(59): signal "count2" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at zhiyin.vhd(543): signal "count3" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: Using design file key_xuange.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: key_xuange-xuange
Info: Found entity 1: key_xuange
Info: Elaborating entity "key_xuange" for hierarchy "key_xuange:inst14"
Warning: Using design file maoci.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: maoci-mao
Info: Found entity 1: maoci
Info: Elaborating entity "maoci" for hierarchy "maoci:inst1"
Info: Duplicate registers merged to single register
Info: Duplicate register "zhilv:inst|sound" merged to single register "zhilv:inst|count4"
Info: Duplicate registers merged to single register
Info: Duplicate register "key_xuange:inst14|count1" merged to single register "key_xuange:inst14|enable", power-up level changed
Warning: Created node "zhiyin:inst9|Mux5~1023" as a ROM by generating altsyncram megafunction to implement register logic with M512 or M4K memory block. Power-up state differs from the original design.
Info: Duplicate registers merged to single register
Info: Duplicate register "zhilv:inst|countss3[0]" merged to single register "zhiyin:inst9|count1[0]"
Info: Duplicate register "zhilv:inst|countss3[1]" merged to single register "zhiyin:inst9|count1[1]"
Info: Inferred 1 megafunctions from design logic
Info: Inferred altsyncram megafunction (OPERATION_MODE=ROM, NUMWORDS_A=1024, WIDTH_A=5) from the following design logic: "zhiyin:inst9|Mux5~1023"
Info: Found 1 design units, including 1 entities, in source file ../altera/libraries/megafunctions/altsyncram.tdf
Info: Found entity 1: altsyncram
Info: Elaborated megafunction instantiation "zhiyin:inst9|altsyncram:Mux5_rtl_0"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_mau.tdf
Info: Found entity 1: altsyncram_mau
Info: Implemented 423 device resources after synthesis - the final resource count might be different
Info: Implemented 2 input pins
Info: Implemented 1 output pins
Info: Implemented 415 logic cells
Info: Implemented 5 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 8 warnings
Info: Processing ended: Mon Jan 14 15:33:47 2002
Info: Elapsed time: 00:00:14
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