gdb-6.1-bdm-m68k.patch

WaitForSingleObject 摩托罗拉的68k源程序

+  NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
+  NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
+};
+
+static const char *cf_reg_names[NUM_REGS] = {
+  "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
+  "a0", "a1", "a2", "a3", "a4", "a5", "fp", "sp",
+  "ps", "pc",
+  NULL, NULL, NULL, NULL, NULL, NULL, NULL,
+  "vbr",
+  "cacr", "acr0", "acr1", "rambar",
+  "mbar",
+  NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
+  "csr", "aatr", "tdr", "pbr", "pbmr", "abhr", "ablr", "dbr", "dbmr",
+};
+
+static const char *cf5272_reg_names[NUM_REGS] = {
+  "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
+  "a0", "a1", "a2", "a3", "a4", "a5", "fp", "sp",
+  "ps", "pc",
+  NULL, NULL, NULL, NULL, NULL, NULL, NULL,
+  "vbr",
+  "cacr", "acr0", "acr1", "rambar",
+  "mbar",
+  "macsr", "mask", "acc", NULL, NULL, NULL, NULL, NULL,
+  "csr", "aatr", "tdr", "pbr", "pbmr", "abhr", "ablr", "dbr", "dbmr",
+};
+
+static const char *cf5282_reg_names[NUM_REGS] = {
+  "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
+  "a0", "a1", "a2", "a3", "a4", "a5", "fp", "sp",
+  "ps", "pc",
+  NULL, NULL, NULL, NULL, NULL, NULL, NULL,
+  "vbr",
+  "cacr", "acr0", "acr1", "rambar",
+  "flashbar",
+  "macsr", "mask", "acc0", "acc1", "acc2", "acc3", "accext01", "accext32",
+  "csr", "aatr", "tdr", "pbr", "pbmr", "abhr", "ablr", "dbr", "dbmr",
+};
+
+static const char **bdm_reg_names = cpu32_reg_names;
+
+const char *bdm_register_name(int i)
+{
+  if ((i < 0) || (i >= NUM_REGS))
+    return NULL;
+  return bdm_reg_names[i];
+}
+
+static int reg_to_dev_num[] = {
+  BDM_REG_SR,    /* 0 */
+  BDM_REG_RPC,
+  BDM_REG_PCC,
+  BDM_REG_USP,
+  BDM_REG_SSP,
+  BDM_REG_SFC,   /* 5 */
+  BDM_REG_DFC,
+  BDM_REG_ATEMP,
+  BDM_REG_FAR,
+  BDM_REG_VBR,
+  BDM_REG_CACR,  /* 10 */
+  BDM_REG_ACR0,
+  BDM_REG_ACR1,
+  BDM_REG_RAMBAR,
+  BDM_REG_MBAR,
+  -1,            /* 15 */
+  -1,
+  -1,
+  -1,
+  -1,
+  -1,
+  -1,
+  -1,
+  BDM_REG_CSR,
+  BDM_REG_AATR,
+  BDM_REG_TDR,
+  BDM_REG_PBR,
+  BDM_REG_PBMR,
+  BDM_REG_ABHR,
+  BDM_REG_ABLR,
+  BDM_REG_DBR,
+  BDM_REG_DBMR
+ };
+
+#define BDM_FREE_PROG_LOADED() \
+do {xfree (bdm_prog_loaded); bdm_prog_loaded = NULL; } while (0)
+
+/*
+ * The name of the most recently loaded program
+ */
+static char *bdm_prog_loaded;
+
+/*
+ * Do not load the program when creating the target if set to 1.
+ */
+static int bdm_no_load;
+
+/*
+ * Default delay for interface
+ */
+#define  BDM_DEFAULT_DELAY  0
+static int bdm_delay = -1;
+
+/*
+ * does gdb wait or not, only valid for a Coldfire processor
+ */
+static int bdm_gdb_no_wait = 0;
+
+/*
+ * Hold BDM ATEMP register (CPU32 only).
+ */
+static unsigned long atemp;
+static int have_atemp;
+
+/*
+ * Target hit a watchpoint.
+ */
+static int hit_watchpoint;
+
+/*
+ * CF BDM Debug hardware version number.
+ */
+
+static unsigned long cf_debug_ver;
+
+/*
+ * Have we set a debug level.
+ */
+static int bdm_debug_level;
+/*
+ * Not sure if this is defined somewhere. Cannot see anywhere.
+ */
+extern int (*ui_loop_hook) (int);
+
+/*
+ * give target time to come up after reset
+ * time in usec
+ */
+#define  TIME_TO_COME_UP  60000
+
+/*
+ * We are quitting, so do not call error and therefore
+ * jump back into the main event handler.
+ */
+static int bdm_gdb_is_quitting;
+
+static void bdm_close (int quitting);
+
+/*
+ * The load processor.
+ */
+static void bdm_load (char *filename, int from_tty);
+
+/*
+ * Our pid.
+ */
+ptid_t bdm_ptid;
+
+/*
+ * The breakpoint codes for the different processors
+ */
+static char cpu32_breakpoint[] = {0x4a, 0xfa};
+static char cf_breakpoint[] = {0x4a, 0xc8};
+static char *breakpointCode;
+static int breakpointSize;
+
+/*
+ * Display error message and jump back to main input loop
+ */
+static void
+bdm_report_error (void)
+{
+  if (!bdm_gdb_is_quitting)
+    error ("BDM driver error: %s", bdmErrorString ());
+}
+
+/*
+ * The following routines handle the Coldfire hardware breakpoints.  Only one
+ * breakpoint supported so far, and it can be either a PC breakpoint or an
+ * address watchpoint.  Unfortunately, the TARGET_CAN_USE_HARDWARE_WATCHPOINT
+ * macro only allows for bounds checking within one of the two types and not
+ * limits that cover the sum of both, so extra work is needed.
+ *
+ * (Actually, very few processors seem to have much support for that routine
+ * at all.)
+ *
+ * As a result, the way this is handled is that the can_use routine will allow
+ * the first breakpoint of either type to be added.  Any further checking so
+ * that only one of the two can be used is done later when GDB actually tries
+ * to create the breakpoints, usually when the processor is restarted.
+ *
+ * We keep a local copy of the breakpoints list becasue the chain that GDB
+ * keeps isn't exported globally.
+ *
+ * While things could be simplified with only one breakpoint present, setting
+ * up more general routines allows for later expansion if newer versions of
+ * the ColdFire chip support more breakpoints at once.
+ *
+ * Also, the ColdFire supports things like multi-level triggers and triggers
+ * based on the data bus instead of just the address bus.  The GDB commands
+ * don't allow for access to this, but much of it isn't necessary anyway,
+ * as GDB has its own method of handling 'breakpoint conditions' that is
+ * sufficient for most tasks.
+ */
+
+#define TDR_TRC_DDATA 0x00000000
+#define TDR_TRC_HALT  0x40000000
+#define TDR_TRC_DINT  0x80000000
+#define TDR_L2_EBL    0x20000000
+#define TDR_L2_ALL    0x1FFF0000
+#define TDR_L2_EDLW   0x10000000
+#define TDR_L2_EDWL   0x08000000
+#define TDR_L2_EDWU   0x04000000
+#define TDR_L2_EDLL   0x02000000
+#define TDR_L2_EDLM   0x01000000
+#define TDR_L2_EDUM   0x00800000
+#define TDR_L2_EDUU   0x00400000
+#define TDR_L2_DI     0x00200000
+#define TDR_L2_EAI    0x00100000
+#define TDR_L2_EAR    0x00080000
+#define TDR_L2_EAL    0x00040000
+#define TDR_L2_EPC    0x00020000
+#define TDR_L2_PCI    0x00010000
+#define TDR_L1_EBL    0x00002000
+#define TDR_L1_ALL    0x00001FFF
+#define TDR_L1_EDLW   0x00001000
+#define TDR_L1_EDWL   0x00000800
+#define TDR_L1_EDWU   0x00000400
+#define TDR_L1_EDLL   0x00000200
+#define TDR_L1_EDLM   0x00000100
+#define TDR_L1_EDUM   0x00000080
+#define TDR_L1_EDUU   0x00000040
+#define TDR_L1_DI     0x00000020
+#define TDR_L1_EAI    0x00000010
+#define TDR_L1_EAR    0x00000008
+#define TDR_L1_EAL    0x00000004
+#define TDR_L1_EPC    0x00000002
+#define TDR_L1_PCI    0x00000001
+
+struct cf_break  {
+  enum target_hw_bp_type type;
+  CORE_ADDR   addr;
+  int         len;
+};
+
+#define CF_BREAKPOINT_MAX 1
+
+static struct cf_break cf_breakpoints[CF_BREAKPOINT_MAX];
+static int cf_breakpoint_count;
+
+static int
+cf_init_watchpoints(void)
+{
+  if (cpu_type != BDM_COLDFIRE)  {
+    return(-1);
+  }
+  cf_breakpoint_count = 0;
+  if (bdmWriteSystemRegister (BDM_REG_TDR, TDR_TRC_HALT) < 0)
+    bdm_report_error ();
+  return(0);
+}
+
+int
+cf_stopped_by_watchpoint(void)
+{
+  return hit_watchpoint;
+}
+
+int
+cf_can_use_watchpoint(enum target_hw_bp_type type, int cnt, int ot)
+{
+  unsigned long tdr;
+
+  if (cpu_type != BDM_COLDFIRE)  {
+    return(0);
+  }
+
+  if (type == bp_hardware_breakpoint || type == bp_read_watchpoint ||
+      type == bp_hardware_watchpoint || type == bp_access_watchpoint)  {
+    if (cnt <= 1)  {
+      return(1);
+    }
+  }
+
+  return(-1);
+}
+
+int
+cf_insert_hw_breakpoint(CORE_ADDR addr, char *shadow)
+{
+  unsigned long tdr;
+
+  if (cpu_type != BDM_COLDFIRE)  {
+    return(-1);
+  }
+
+  if (cf_breakpoint_count < CF_BREAKPOINT_MAX)  {
+    cf_breakpoints[cf_breakpoint_count].type = hw_execute;
+    cf_breakpoints[cf_breakpoint_count].addr = addr;
+    cf_breakpoints[cf_breakpoint_count++].len = 2;
+
+    if (bdmReadSystemRegister (BDM_REG_TDR, &tdr) < 0)
+      bdm_report_error ();
+    tdr = ((tdr & ~TDR_L1_ALL) | (TDR_L1_EBL|TDR_L1_EPC));
+    if (bdmWriteSystemRegister (BDM_REG_PBR, addr) < 0)
+      bdm_report_error ();
+    if (bdmWriteSystemRegister (BDM_REG_PBMR, 0) < 0)
+      bdm_report_error ();
+    if (bdmWriteSystemRegister (BDM_REG_TDR, tdr) < 0)
+      bdm_report_error ();
+    if (bdm_debug_level)
+      printf_filtered ("Insert PC Breakpoint @0x%08lx\n", addr);
+  }
+  else  {
+    return(-1);
+  }
+  return(0);
+}
+
+static int
+cf_check_breakpoint(type, addr, len)
+  enum target_hw_bp_type type;
+  CORE_ADDR addr;
+  int len;
+{
+  int i;
+
+  for (i = 0; i < cf_breakpoint_count; i++)  {
+    if (cf_breakpoints[i].type == type &&
+        cf_breakpoints[i].addr == addr &&
+        cf_breakpoints[i].len == len)  {
+      for (; i < CF_BREAKPOINT_MAX-1; i++)  {
+        cf_breakpoints[i] = cf_breakpoints[i+1];
+      }
+      cf_breakpoint_count--;
+      return(1);
+    }
+  }
+  return(0);
+}
+
+int
+cf_remove_hw_breakpoint(CORE_ADDR addr, char *shadow)
+{
+  unsigned long tdr;
+  unsigned long csr;
+
+  if (cpu_type != BDM_COLDFIRE)  {
+    return(-1);
+  }
+
+  if (cf_check_breakpoint(hw_execute, addr, 2))  {
+    if (bdmReadSystemRegister (BDM_REG_TDR, &tdr) < 0)
+      bdm_report_error ();
+    tdr &= ~TDR_L1_EPC;
+    if ((tdr & TDR_L1_ALL) == 0)  {
+      tdr &= ~TDR_L1_EBL;
+    }
+    if (bdmWriteSystemRegister (BDM_REG_TDR, tdr) < 0)
+      bdm_report_error ();
+    if (bdm_debug_level)
+      printf_filtered ("Remove PC Breakpoint @0x%08lx\n", addr);
+  }
+  else  {
+    return(-1);
+  }
+  return(0);
+}
+
+#define AATR_READONLY  0x7F85
+#define AATR_WRITEONLY 0x7F05
+#define AATR_READWRITE 0xFF05
+
+int
+cf_insert_watchpoint(CORE_ADDR addr, int len, enum target_hw_bp_type type)
+{
+  unsigned long tdr;
+
+  if (cpu_type != BDM_COLDFIRE)  {
+    return(-1);
+  }
+
+  if (cf_breakpoint_count < CF_BREAKPOINT_MAX)  {
+    cf_breakpoints[cf_breakpoint_count].type = type;
+    cf_breakpoints[cf_breakpoint_count].addr = addr;
+    cf_breakpoints[cf_breakpoint_count++].len = len;
+
+    if (bdmReadSystemRegister (BDM_REG_TDR, &tdr) < 0)
+      bdm_report_error ();
+    tdr = ((tdr & ~TDR_L1_ALL) | (TDR_L1_EBL|TDR_L1_EAR));
+    if (bdmWriteSystemRegister (BDM_REG_ABLR, addr) < 0)
+      bdm_report_error ();
+    if (bdmWriteSystemRegister (BDM_REG_ABHR, addr+len-1) < 0)
+      bdm_report_error ();
+    if (type == hw_read)  {
+      if (bdmWriteSystemRegister (BDM_REG_AATR, AATR_READONLY) < 0)
+        bdm_report_error ();
+      if (bdm_debug_level)
+        printf_filtered ("Insert read Watchpoint @0x%08lx-0x%08lx\n",
+                         addr, addr+len-1);
+    }
+    else if (type == hw_write)  {
+      if (bdmWriteSystemRegister (BDM_REG_AATR, AATR_WRITEONLY) < 0)
+        bdm_report_error ();
+      if (bdm_debug_level)
+        printf_filtered ("Insert write Watchpoint @0x%08lx-0x%08lx\n",
+                         (long unsigned int)addr, addr+len-1);
+    }
+    else  {
+      if (bdmWriteSystemRegister (BDM_REG_AATR, AATR_READWRITE) < 0)
+        bdm_report_error ();
+      if (bdm_debug_level)
+        printf_filtered ("Insert access Watchpoint @0x%08lx-0x%08lx\n",
+                         addr, addr+len-1);
+    }
+    if (bdmWriteSystemRegister (BDM_REG_TDR, tdr) < 0)
+      bdm_report_error ();
+  }
+  else  {
+    return(-1);
+  }
+  return(0);
+}
+
+int
+cf_remove_watchpoint(CORE_ADDR addr, int len, enum target_hw_bp_type type)
+{
+  unsigned long tdr;
+  unsigned long csr;
+
+  if (cpu_type != BDM_COLDFIRE)  {
+    return(-1);
+  }
+
+  if (cf_check_breakpoint(type, addr, len))  {
+    if (bdmReadSystemRegister (BDM_REG_TDR, &tdr) < 0)
+      bdm_report_error ();
+    tdr &= ~TDR_L1_EAR;
+    if ((tdr & TDR_L1_ALL) == 0)  {
+      tdr &= ~TDR_L1_EBL;
+    }