📄 mcbsp.h
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/*----------------------------------------------------------------------------*/
#define DATA_DELAY0 0x00 /* 1st bit in same clk period as fsync */
#define DATA_DELAY1 0x01 /* 1st bit 1 clk period after fsync */
#define DATA_DELAY2 0x02 /* 1st bit 2 clk periods after fsync */
/******************************************************************************/
/* Multi-channel Transmit Control Register 1 Bits(XCR1) */
/******************************************************************************/
/* +-0f-+-0e-08-+-07-05-+-04-00--+ */
/* |rsvd|XFRLEN1|XWDLEN1|RESERVED| */
/* +----+-------+-------+--------+ */
/******************************************************************************/
#define XFRLEN1 0x08
#define XWDLEN1 0x05
#define XFRLEN1_SZ 0x07
#define XWDLEN1_SZ 0x03
/******************************************************************************/
/* Multi-channel Transmit Control Register 2 Bits(XCR2) */
/******************************************************************************/
/* +--0f--+-0e-08-+-07-05-+-04-03--+-02-+-01-00-+ */
/* |XPHASE|XFRLEN2|XWDLEN2|XCOMPAND|XFIG|XDATDLY| */
/* +------+-------+-------+--------+----+-------+ */
/******************************************************************************/
#define XPHASE 0x0F
#define XFRLEN2 0x08
#define XWDLEN2 0x05
#define XCOMPAND 0x03
#define XFIG 0x02
#define XDATDLY 0x00
#define XPHASE_SZ 0x01
#define XFRLEN2_SZ 0x07
#define XWDLEN2_SZ 0x03
#define XCOMPAND_SZ 0x02
#define XFIG_SZ 0x01
#define XDATDLY_SZ 0x02
/******************************************************************************/
/* Multi-channel Sample Rate Generator Register 1 Bits(SRGR1) */
/******************************************************************************/
/* +-0f-08-+-07--00-+ */
/* | FWID | CLKGDV | */
/* +-------+--------+ */
/******************************************************************************/
#define FWID 0x08
#define CLKGDV 0x00
#define FWID_SZ 0x08
#define CLKGDV_SZ 0x08
/*----------------------------------------------------------------------------*/
/* CLKGDV */
/*----------------------------------------------------------------------------*/
#define MAX_SRG_CLK_DIV 0xFF /* max value to divide Sample Rate Gen Cl*/
/*----------------------------------------------------------------------------*/
/* FWID */
/*----------------------------------------------------------------------------*/
#define MAX_FRAME_WIDTH 0xFF /* maximum FSG width in CLKG periods */
/******************************************************************************/
/* Multi-channel Sample Rate Generator Register 2 Bits(SRGR2) */
/******************************************************************************/
/* +--0f-+--0e-+--0d-+-0c-+-0b--00-+ */
/* |GSYNC|CLKSP|CLKSM|FSGM| FPER | */
/* +-----+-----+-----+----+--------+ */
/******************************************************************************/
#define GSYNC 0x0F
#define CLKSP 0x0E
#define CLKSM 0x0D
#define FSGM 0x0C
#define FPER 0x00
#define GSYNC_SZ 0x01
#define CLKSP_SZ 0x01
#define CLKSM_SZ 0x01
#define FSGM_SZ 0x01
#define FPER_SZ 0x0C
/*----------------------------------------------------------------------------*/
/* FPER */
/*----------------------------------------------------------------------------*/
#define MAX_FRAME_PERIOD 0x0FFF /* FSG period in CLKG periods */
/*----------------------------------------------------------------------------*/
/* FSGM */
/*----------------------------------------------------------------------------*/
#define FSX_DXR_TO_XSR 0x00 /* Transmit FSX due to DXR to XSR copy */
#define FSX_FSG 0x01 /* Transmit FSX due to FSG */
/*----------------------------------------------------------------------------*/
/* CLKSM */
/*----------------------------------------------------------------------------*/
#define CLK_MODE_CLKS 0x00 /* Clock derived from CLKS source */
#define CLK_MODE_CPU 0x01 /* Clock derived from CPU clock source */
/*----------------------------------------------------------------------------*/
/* CLKSM? */
/*----------------------------------------------------------------------------*/
#define CLK_MODE_BCLKR 0x00 /* Clock derived from BCLKR source */
#define CLK_MODE_BCLKX 0x01 /* Clock derived from BCLKX source */
/*----------------------------------------------------------------------------*/
/* CLKSP */
/*----------------------------------------------------------------------------*/
#define CLKS_POL_FALLING 0x01 /* falling edge generates CLKG and FSG */
#define CLKS_POL_RISING 0x00 /* rising edge generates CLKG and FSG */
/*----------------------------------------------------------------------------*/
/* GSYNC */
/*----------------------------------------------------------------------------*/
#define GSYNC_OFF 0x00 /* CLKG always running */
#define GSYNC_ON 0x01 /* CLKG and FSG synched to FSR */
/******************************************************************************/
/* Multi-channel Multichannel Control Register 1 Bits(MCR1) */
/******************************************************************************/
/* +-0f--09-+-08--07-+-06--05-+-04-02-+-01-+-00-+ */
/* | rsvd | RPBBLK | RPABLK | RCBLK |rsvd|RMCM| */
/* +--------+--------+--------+-------+----+----+ */
/******************************************************************************/
#define RPBBLK 0x07
#define RPABLK 0x05
#define RCBLK 0x02
#define RMCM 0x00
#define RPBBLK_SZ 0x02
#define RPABLK_SZ 0x02
#define RCBLK_SZ 0x03
#define RMCM_SZ 0x01
/******************************************************************************/
/* Multi-channel Multichannel Control Register 2 Bits(MCR2) */
/******************************************************************************/
/* +-0f--09-+-08--07-+-06--05-+-04-02-+-01--00-+ */
/* | rsvd | XPBBLK | XPABLK | XCBLK | XMCM | */
/* +--------+--------+--------+-------+--------+ */
/******************************************************************************/
#define XPBBLK 0x07
#define XPABLK 0x05
#define XCBLK 0x02
#define XMCM 0x00
#define XPBBLK_SZ 0x02
#define XPABLK_SZ 0x02
#define XCBLK_SZ 0x03
#define XMCM_SZ 0x02
/******************************************************************************/
/* Multi-channel Receive Channel Enable Register Partition A Bits(RCERA) */
/******************************************************************************/
/* +--0f---+--0e---+--0d---+--0c---+--0b---+--0a---+--09--+--08--+ */
/* |RCERA15|RCERA14|RCERA13|RCERA12|RCERA11|RCERA10|RCERA9|RCERA8| */
/* +-------+-------+-------+-------+-------+-------+------+------+ */
/* +--07--+--06--+--05--+--04--+--03--+--02--+--01--+--00--+ */
/* |RCERA7|RCERA6|RCERA5|RCERA4|RCERA3|RCERA2|RCERA1|RCERA0| */
/* +------+------+------+------+------+------+------+------+ */
/******************************************************************************/
/******************************************************************************/
/* Multi-channel Receive Channel Enable Register Partition B Bits(RCERB) */
/******************************************************************************/
/* +--0f---+--0e---+--0d---+--0c---+--0b---+--0a---+--09--+--08--+ */
/* |RCERB15|RCERB14|RCERB13|RCERB12|RCERB11|RCERB10|RCERB9|RCERB8| */
/* +-------+-------+-------+-------+-------+-------+------+------+ */
/* +--07--+--06--+--05--+--04--+--03--+--02--+--01--+--00--+ */
/* |RCERB7|RCERB6|RCERB5|RCERB4|RCERB3|RCERB2|RCERB1|RCERB0| */
/* +------+------+------+------+------+------+------+------+ */
/******************************************************************************/
/******************************************************************************/
/* Multi-channel Transmit Channel Enable Register Partition A Bits(XCERA) */
/******************************************************************************/
/* +--0f---+--0e---+--0d---+--0c---+--0b---+--0a---+--09--+--08--+ */
/* |RCERA15|RCERA14|RCERA13|RCERA12|RCERA11|RCERA10|RCERA9|RCERA8| */
/* +-------+-------+-------+-------+-------+-------+------+------+ */
/* +--07--+--06--+--05--+--04--+--03--+--02--+--01--+--00--+ */
/* |RCERA7|RCERA6|RCERA5|RCERA4|RCERA3|RCERA2|RCERA1|RCERA0| */
/* +------+------+------+------+------+------+------+------+ */
/******************************************************************************/
/******************************************************************************/
/* Multi-channel Transmit Channel Enable Register Partition B Bits(XCERB) */
/******************************************************************************/
/* +--0f---+--0e---+--0d---+--0c---+--0b---+--0a---+--09--+--08--+ */
/* |RCERB15|RCERB14|RCERB13|RCERB12|RCERB11|RCERB10|RCERB9|RCERB8| */
/* +-------+-------+-------+-------+-------+-------+------+------+ */
/* +--07--+--06--+--05--+--04--+--03--+--02--+--01--+--00--+ */
/* |RCERB7|RCERB6|RCERB5|RCERB4|RCERB3|RCERB2|RCERB1|RCERB0| */
/* +------+------+------+------+------+------+------+------+ */
/******************************************************************************/
/******************************************************************************/
/* Multi-channel Pin Control Register Bits(PCR) */
/******************************************************************************/
/* +-0f-0e-+--0d-+--0c-+-0b-+-0a-+--09-+--08-+ */
/* | rsvd |XIOEN|RIOEN|FSXM|FSRM|CLKXM|CLKRM| */
/* +-------+-----+-----+----+----+-----+-----+ */
/* +-07-+---06----+--05---+--04---+-03-+-02-+--01-+--00-+ */
/* |rsvd|CLKS_STAT|DX_STAT|DR_STAT|FSXP|FSRP|CLKXP|CLKRP| */
/* +----+---------+-------+-------+----+----+-----+-----+ */
/******************************************************************************/
#define XIOEN 0x0D
#define RIOEN 0x0C
#define FSXM 0x0B
#define FSRM 0x0A
#define CLKXM 0x09
#define CLKRM 0x08
#define CLKS_STAT 0x06
#define DX_STAT 0x05
#define DR_STAT 0x04
#define FSXP 0x03
#define FSRP 0x02
#define CLKXP 0x01
#define CLKRP 0x00
#define XIOEN_SZ 0x01
#define RIOEN_SZ 0x01
#define FSXM_SZ 0x01
#define FSRM_SZ 0x01
#define CLKXM_SZ 0x01
#define CLKRM_SZ 0x01
#define CLKS_STAT_SZ 0x01
#define DX_STAT_SZ 0x01
#define DR_STAT_SZ 0x01
#define FSXP_SZ 0x01
#define FSRP_SZ 0x01
#define CLKXP_SZ 0x01
#define CLKRP_SZ 0x01
/*----------------------------------------------------------------------------*/
/* CLKRP */
/*----------------------------------------------------------------------------*/
#define CLKR_POL_RISING 0x01 /* R Data Sampled on Rising Edge of CLKR */
#define CLKR_POL_FALLING 0x00 /* R Data Sampled on Falling Edge of CLKR*/
/*----------------------------------------------------------------------------*/
/* CLKXP */
/*----------------------------------------------------------------------------*/
#define CLKX_POL_RISING 0x00 /* X Data Sent on Rising Edge of CLKX */
#define CLKX_POL_FALLING 0x01 /* X Data Sent on Falling Edge of CLKX */
/*----------------------------------------------------------------------------*/
/* FSXP/FSRP */
/*----------------------------------------------------------------------------*/
#define FSYNC_POL_HIGH 0x00 /* Frame Sync Pulse Active High */
#define FSYNC_POL_LOW 0x01 /* Frame Sync Pulse Active Low */
/*----------------------------------------------------------------------------*/
/* CLKRM/CLKXM */
/*----------------------------------------------------------------------------*/
#define CLK_MODE_EXT 0x00 /* Clock derived from external source */
#define CLK_MODE_INT 0x01 /* Clock derived from internal source */
/*----------------------------------------------------------------------------*/
/* FSRM/FSXM */
/*----------------------------------------------------------------------------*/
#define FSYNC_MODE_EXT 0x00 /* Frame Sync derived from external src */
#define FSYNC_MODE_INT 0x01 /* Frame Sync dervived from internal src */
/*----------------------------------------------------------------------------*/
/* XIOEN/RIOEN */
/*----------------------------------------------------------------------------*/
#define MCBSP_IO_MODE 0x01 /* MCBSP IO mode enable */
#define MCBSP_SERIAL_MODE 0x00 /* MCBSP SERIAL mode enable */
/*----------------------------------------------------------------------------*/
/* FSXP/FSRP/CLKXP/CLKRP */
/*----------------------------------------------------------------------------*/
#define IO_HIGH 0x01 /* */
#define IO_LOW 0x00 /* */
/******************************************************************************/
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