📄 mcbsp.h
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/******************************************************************************/
/* mcbsp.h */
/* */
/* This is proprietary information, not to be published -- DIGIPRO DATA */
/* Copyright (C) 2002, DigiPro Information Co.,Ltd. All Rights Reserved. */
/* */
/* Author: Wu DingMing */
/* Date: August 12, 2002 */
/******************************************************************************/
#include "regs.h"
#include "mmdrv.h"
/******************************************************************************/
/* MCBSP Registers $ */
/******************************************************************************/
#define MCBSP_ADDR(port) (0x020 + ((port)*0x08))+(((port)%2)*0x18)
#define MCBSP_DRR2_ADDR(port) (MCBSP_ADDR(port))
#define MCBSP_DRR1_ADDR(port) ((MCBSP_ADDR(port)) + 0x01)
#define MCBSP_DXR2_ADDR(port) ((MCBSP_ADDR(port)) + 0x02)
#define MCBSP_DXR1_ADDR(port) ((MCBSP_ADDR(port)) + 0x03)
#define MCBSP_SPSA_ADDR(port) (0x38 + (((port)%2)*0x10) - ((port/2)*0x04))
#define MCBSP_SPAD_ADDR(port) (0x39 + (((port)%2)*0x10) - ((port/2)*0x04))
#define MCBSP_DRR2(port) *(volatile unsigned int *)(MCBSP_DRR2_ADDR(port))
#define MCBSP_DRR1(port) *(volatile unsigned int *)(MCBSP_DRR1_ADDR(port))
#define MCBSP_DXR2(port) *(volatile unsigned int *)(MCBSP_DXR2_ADDR(port))
#define MCBSP_DXR1(port) *(volatile unsigned int *)(MCBSP_DXR1_ADDR(port))
#define MCBSP_SPSA(port) *(volatile unsigned int *)(MCBSP_SPSA_ADDR(port))
#define MCBSP_SPAD(port) *(volatile unsigned int *)(MCBSP_SPAD_ADDR(port))
#define MCBSP_SET(port,add,data) MCBSP_SPSA(port) = add, MCBSP_SPAD(port) = data
#define MCBSP0_SET(add,data) MCBSP0_SPSA = add, MCBSP0_SPAD = data
#define MCBSP1_SET(add,data) MCBSP1_SPSA = add, MCBSP1_SPAD = data
#define MCBSP2_SET(add,data) MCBSP2_SPSA = add, MCBSP2_SPAD = data
#define MCBSP_SETBIT(port,add,val,bit,lenth) \
MCBSP_SPSA(port) = add, LOAD_FIELD(MCBSP_SPAD_ADDR(port), val,bit,lenth)
#define MCBSP0_SETBIT(add,val,bit,lenth) \
MCBSP0_SPSA = add, LOAD_FIELD(MCBSP0_SPAD_ADDR, val,bit,lenth)
#define MCBSP1_SETBIT(add,val,bit,lenth) \
MCBSP1_SPSA = add, LOAD_FIELD(MCBSP1_SPAD_ADDR, val,bit,lenth)
#define MCBSP2_SETBIT(add,val,bit,lenth) \
MCBSP2_SPSA = add, LOAD_FIELD(MCBSP2_SPAD_ADDR, val,bit,lenth)
#define MCBSP2_GETBIT(add,val,bit,lenth) \
MCBSP2_SPSA = add, val = GET_FIELD(MCBSP2_SPAD_ADDR, bit,lenth)
/******************************************************************************/
/* MCBSP Sub Registers */
/******************************************************************************/
#define MCBSP_SPCR1_SUBADDR 0x00
#define MCBSP_SPCR2_SUBADDR 0x01
#define MCBSP_RCR1_SUBADDR 0x02
#define MCBSP_RCR2_SUBADDR 0x03
#define MCBSP_XCR1_SUBADDR 0x04
#define MCBSP_XCR2_SUBADDR 0x05
#define MCBSP_SRGR1_SUBADDR 0x06
#define MCBSP_SRGR2_SUBADDR 0x07
#define MCBSP_MCR1_SUBADDR 0x08
#define MCBSP_MCR2_SUBADDR 0x09
#define MCBSP_RCERA_SUBADDR 0x0a
#define MCBSP_RCERB_SUBADDR 0x0b
#define MCBSP_XCERA_SUBADDR 0x0c
#define MCBSP_XCERB_SUBADDR 0x0d
#define MCBSP_PCR_SUBADDR 0x0e
/******************************************************************************/
/* Multi-channel Serial Port Control Register 1 Bits(SPCR1) */
/******************************************************************************/
/* +-0f-+-0e-0d-+-0c--0b-+-0a-08-+-07--+-06-+-05-04-+---03---+-02--+-01-+-00-+*/
/* | DLB| RJUST | CLKSTP | RSVD |DXENA|ABIS| RINTM |RSYNCERR|RFULL|RRDY|RRST|*/
/* +----+-------+--------+-------+-----+----+-------+--------+-----+----+----+*/
/******************************************************************************/
#define DLB 0x0F
#define RJUST 0x0D
#define CLKSTP 0x0B
#define DXENA 0x07
#define ABIS 0x06
#define RINTM 0x04
#define RSYNCERR 0x03
#define RFULL 0x02
#define RRDY 0x01
#define RRST 0x00
#define DLB_SZ 0x01
#define RJUST_SZ 0x02
#define CLKSTP_SZ 0x02
#define DXENA_SZ 0x01
#define ABIS_SZ 0x01
#define RINTM_SZ 0x02
#define RSYNCERR_SZ 0x01
#define RFULL_SZ 0x01
#define RRDY_SZ 0x01
#define RRST_SZ 0x01
/*----------------------------------------------------------------------------*/
/* DLB */
/*----------------------------------------------------------------------------*/
#define RXJUST_RJZF 0x00 /* Receive Right Justify Zero Fill */
#define RXJUST_RJSE 0x01 /* Receive Right Justify Sign Extend */
#define RXJUST_LJZF 0x02 /* Receive Left Justify Zero Fill */
/*----------------------------------------------------------------------------*/
/* RJUST */
/*----------------------------------------------------------------------------*/
#define DLB_ENABLE 0x01 /* Enable Digital Loopback Mode */
#define DLB_DISABLE 0x00 /* Disable Digital Loopback Mode */
/*----------------------------------------------------------------------------*/
/* CLKSTP */
/*----------------------------------------------------------------------------*/
#define CLKSTP_NOSTOP 0x00 /* Clock stop mode disabled.non_SPI mode */
#define CLKSTP_STARTNODLY 0x02 /* Clock start with edge without delay */
#define CLKSTP_STARTDLY 0x03 /* Clock start with edge with delay */
/*----------------------------------------------------------------------------*/
/* DXENA */
/*----------------------------------------------------------------------------*/
#define DX_ENABLE_OFF 0 /* DX enable is off */
#define DX_ENABLE_ON 1 /* DX enable is on */
/*----------------------------------------------------------------------------*/
/* ABIS */
/*----------------------------------------------------------------------------*/
#define ABIS_MODE_DISABLE 0 /* Disable ABIS Mode */
#define ABIS_MODE_ENABLE 1 /* Enable ABIS Mode */
/*----------------------------------------------------------------------------*/
/* RINTM/XINTM */
/*----------------------------------------------------------------------------*/
#define INTM_RDY 0x00 /* R/X INT driven by R/X RDY */
#define INTM_BLOCK 0x01 /* R/X INT driven by new multichannel blk*/
#define INTM_FRAME 0x02 /* R/X INT driven by new frame sync */
#define INTM_SYNCERR 0x03 /* R/X INT generated by R/X SYNCERR */
/*----------------------------------------------------------------------------*/
/* RSYNCERR/XSYNCERR */
/*----------------------------------------------------------------------------*/
#define SYNC_NOERR 0
#define SYNC_ERR 1
/*----------------------------------------------------------------------------*/
/* RFULL */
/*----------------------------------------------------------------------------*/
#define RBR12_NO_FULL 0
#define RBR12_FULL 1
/*----------------------------------------------------------------------------*/
/* RRDY/XRDY */
/*----------------------------------------------------------------------------*/
#define RX_RDY 1 /* R/X is no ready */
#define RX_NORDY 0 /* R/X is ready with data to be from DRR */
/*----------------------------------------------------------------------------*/
/* RRST/XRST */
/*----------------------------------------------------------------------------*/
#define RX_WORK 1 /* R/X enable */
#define RX_RESET 0 /* R/X disable and in reset state */
/******************************************************************************/
/* Multi-channel Serial Port Control Register 2 Bits(SPCR2) */
/******************************************************************************/
/* +0f-0a+-09-+-08-+-07--+-06--+-05-04-+---03---+--02--+-01-+-00-+ */
/* | rsvd|FREE|SOFT|/FRST|/GRST| XINTM |XSYNCERR|XEMPTY|XRDY|XRST| */
/* +-----+----+----+-----+-----+-------+--------+------+----+----+ */
/******************************************************************************/
#define FREE 9
#define SOFT 8
#define FRST 07
#define GRST 06
#define XINTM 04
#define XSYNCERR 03
#define XEMPTY 02
#define XRDY 01
#define XRST 00
#define FREE_SZ 01
#define SOFT_SZ 01
#define FRST_SZ 01
#define GRST_SZ 01
#define XINTM_SZ 02
#define XSYNCERR_SZ 01
#define XEMPTY_SZ 01
#define XRDY_SZ 01
#define XRST_SZ 01
/*----------------------------------------------------------------------------*/
/* FREE */
/*----------------------------------------------------------------------------*/
#define FREE_MODE_DISABLE 0 /* Free running mode is disable */
#define FREE_MODE_ENABLE 1 /* Free running mode is enable */
/*----------------------------------------------------------------------------*/
/* SOFT */
/*----------------------------------------------------------------------------*/
#define SOFT_MODE_DISABLE 0 /* Soft mode is disable */
#define SOFT_MODE_ENABLE 1 /* Soft mode is enable */
/*----------------------------------------------------------------------------*/
/* FRST */
/*----------------------------------------------------------------------------*/
#define FRAME_SYNC_RESET 0 /* Frame-sync logic is reset */
#define FRAME_SYNC_WORK 1 /* Frame-sync logic is generatesd */
/*----------------------------------------------------------------------------*/
/* GRST */
/*----------------------------------------------------------------------------*/
#define SR_GENERATOR_RESET 0 /* Sample_rate generator is reset */
#define SR_GENERATOR_WORK 1 /* Sample_rate generator is generatesd */
/*----------------------------------------------------------------------------*/
/* XEMPTY */
/*----------------------------------------------------------------------------*/
#define XSR12_EMPTY 0 /* XSR[1,2] is empty */
#define XSR12_NO_EMPTY 1 /* XSR[1,2] is not empty */
/******************************************************************************/
/* Multi-channel Receive Control Register 1 Bits(RCR1) */
/******************************************************************************/
/* +-0f-+-0e-08-+-07-05-+-04-00--+ */
/* |rsvd|RFRLEN1|RWDLEN1|RESERVED| */
/* +----+-------+-------+--------+ */
/******************************************************************************/
#define RFRLEN1 0x08
#define RWDLEN1 0x05
#define RFRLEN1_SZ 0x07
#define RWDLEN1_SZ 0x03
/*----------------------------------------------------------------------------*/
/* RFRLEN1/2/XFRLEN1/2 */
/*----------------------------------------------------------------------------*/
#define MAX_FRAME_LENGTH 0x7f /* maximum number of words per frame */
/*----------------------------------------------------------------------------*/
/* RWDLEN1/2/XWDLEN1/2 */
/*----------------------------------------------------------------------------*/
#define WORD_LENGTH_8 0x00 /* 8 bit word length (requires filling) */
#define WORD_LENGTH_12 0x01 /* 12 bit word length "" */
#define WORD_LENGTH_16 0x02 /* 16 bit word length "" */
#define WORD_LENGTH_20 0x03 /* 20 bit word length "" */
#define WORD_LENGTH_24 0x04 /* 24 bit word length "" */
#define WORD_LENGTH_32 0x05 /* 32 bit word length (matches DRR DXR sz*/
#define MAX_WORD_LENGTH WORD_LENGTH_32
/******************************************************************************/
/* Multi-channel Receive Control Register 2 Bits(RCR2) */
/******************************************************************************/
/* +--0f--+-0e-08-+-07-05-+-04-03--+-02-+-01-00-+ */
/* |RPHASE|RFRLEN2|RWDLEN2|RCOMPAND|RFIG|RDATDLY| */
/* +------+-------+-------+--------+----+-------+ */
/******************************************************************************/
#define RPHASE 0x0F
#define RFRLEN2 0x08
#define RWDLEN2 0x05
#define RCOMPAND 0x03
#define RFIG 0x02
#define RDATDLY 0x00
#define RPHASE_SZ 0x01
#define RFRLEN2_SZ 0x07
#define RWDLEN2_SZ 0x03
#define RCOMPAND_SZ 0x02
#define RFIG_SZ 0x01
#define RDATDLY_SZ 0x02
/*----------------------------------------------------------------------------*/
/* RPHASE/XPHASE */
/*----------------------------------------------------------------------------*/
#define SINGLE_PHASE 0x00 /* Selects single phase frames */
#define DUAL_PHASE 0x01 /* Selects dual phase frames */
/*----------------------------------------------------------------------------*/
/* RCOMPAND/XCOMPAND */
/*----------------------------------------------------------------------------*/
#define NO_COMPAND_MSB_1ST 0x00 /* No Companding, Data XFER starts w/MSb */
#define NO_COMPAND_LSB_1ST 0x01 /* No Companding, Data XFER starts w/LSb */
#define COMPAND_ULAW 0x02 /* Compand ULAW, 8 bit word length only */
#define COMPAND_ALAW 0x03 /* Compand ALAW, 8 bit word length only */
/*----------------------------------------------------------------------------*/
/* RFIG/XFIG */
/*----------------------------------------------------------------------------*/
#define FRAME_IGNORE 0x01 /* Ignore frame sync pulses after 1st */
#define NO_FRAME_IGNORE 0x00 /* Utilize frame sync pulses */
/*----------------------------------------------------------------------------*/
/* RDATDLY/XDATDLY */
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