📄 adda.h
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/******************************************************************************/
/* adda.h */
/* */
/* This is proprietary information, not to be published -- DIGIPRO DATA */
/* Copyright (C) 2002, DigiPro Information Co.,Ltd. All Rights Reserved. */
/* */
/* Author: Wu DingMing */
/* Date: August 12, 2002 */
/******************************************************************************/
#include "mcbsp.h"
#include "HDdrv.h"
#define SELECT_ADC() ADDA_SELECT = 1
/*MCBSP2_SETBIT(MCBSP_PCR_SUBADDR,IO_HIGH,FSRP,1)*/
#define SELECT_DAC() ADDA_SELECT = 0
/*MCBSP2_SETBIT(MCBSP_PCR_SUBADDR,IO_LOW,FSRP,1)*/
#define CS_ENABLE() SPI_CS = 0
/*MCBSP2_SETBIT(MCBSP_PCR_SUBADDR,IO_LOW,FSXP,1)*/
#define CS_DISABLE() SPI_CS = 1
/*MCBSP2_SETBIT(MCBSP_PCR_SUBADDR,IO_HIGH,FSXP,1)*/
#define CLK_HIGH() MCBSP2_SETBIT(MCBSP_PCR_SUBADDR,IO_HIGH,CLKXP,1)
#define CLK_LOW() MCBSP2_SETBIT(MCBSP_PCR_SUBADDR,IO_LOW,CLKXP,1)
#define OUTPUT_DATA(data) MCBSP2_SETBIT(MCBSP_PCR_SUBADDR,data,DX_STAT,1)
#define INPUT_DATA(data) MCBSP2_GETBIT(MCBSP_PCR_SUBADDR,data,DR_STAT,1)
void Init_MCBSP_To_IO(void);
void Set_ADC(unsigned int data);
unsigned int get_ADC_data(unsigned int data);
unsigned int get_ADC_state(unsigned int data);
void run_DAC(unsigned int data);
/******************************************************************************/
/* DAC-tlv5638 */
/******************************************************************************/
/* DATA FORMAT: 16-bit data word consists of the two parts */
/* ---Program bits(D15--D12) */
/* ---New data(D15--D12) */
/* +D15+-D14-+-D13-+D12+--D11--D0--+ */
/* | R1| SPD | PWM | R0|12 data bit| */
/* +---+-----+-----+---+-----------+ */
/* SPD:Speed Control bit 1-->fast mode 0-->slow mode */
/* PWM:Power Control bit 1-->power down 0-->normal operation */
/* register select bit */
/* +---+---+--------------------------------------------------------+ */
/* | R1| R0| REGISTER | */
/* +---+---+--------------------------------------------------------+ */
/* | 0 | 0 | Write data to DAC B and BUFFER | */
/* +---+---+--------------------------------------------------------+ */
/* | 0 | 1 | Write data to BUFFER | */
/* +---+---+--------------------------------------------------------+ */
/* | 1 | 0 |Write data to DAC A and update DAC B with BUFFER content| */
/* +---+---+--------------------------------------------------------+ */
/* | 1 | 1 | Write data to control register | */
/* +---+---+--------------------------------------------------------+ */
/* data bits: DAC A, DAC B and BUFFER */
/* +-----+-----+----+----+----+----+----+----+----+----+----+----+ */
/* | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | */
/* +-----+-----+----+----+----+----+----+----+----+----+----+----+ */
/* | New DAC Value | */
/* +-----+-----+----+----+----+----+----+----+----+----+----+----+ */
/* data bits: CONTROL */
/* +-----+-----+----+----+----+----+----+----+----+----+----+----+ */
/* | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | */
/* +-----+-----+----+----+----+----+----+----+----+----+----+----+ */
/* | X | X | X | X | X | X | X | X | X | X |REF1|REF0| */
/* +-----+-----+----+----+----+----+----+----+----+----+----+----+ */
/* +----+----+------------------------------------------------------+ */
/* |REF1|REF0| REFERENCE | */
/* +----+----+------------------------------------------------------+ */
/* | 0 | 0 | External | */
/* +----+----+------------------------------------------------------+ */
/* | 0 | 1 | 1.024 V | */
/* +----+----+------------------------------------------------------+ */
/* | 1 | 0 | 2.048 V | */
/* +----+----+------------------------------------------------------+ */
/* | 1 | 1 | External | */
/* +----+----+------------------------------------------------------+ */
/******************************************************************************/
#define DAC_CHANNELA 1
#define DAC_CHANNELB 0
#define DAC_FAST_SPEED 1
#define DAC_SLOW_SPEED 0
#define DAC_EXTERNAL_REF 0
#define DAC_1024V_REF 1
#define DAC_2048V_REF 2
void DAC_single_output(unsigned int channel,unsigned int value,unsigned int ref,unsigned int speed);
void DAC_double_output(unsigned int valueA,unsigned int valueB,unsigned int ref,unsigned int speed);
void DAC_power_down(void);
/******************************************************************************/
/* ADC-tlv2544 */
/******************************************************************************/
/* +------------+------------------------------------------------------+ */
/* |SDI D(15-12)| TLV2544 COMMAND | */
/* +------------+------------------------------------------------------+ */
/* | 0000B | 0H | Select analog input channel 0 | */
/* +------------+------------------------------------------------------+ */
/* | 0010B | 2H | Select analog input channel 1 | */
/* +------------+------------------------------------------------------+ */
/* | 0100B | 4H | Select analog input channel 2 | */
/* +------------+------------------------------------------------------+ */
/* | 0110B | 6H | Select analog input channel 3 | */
/* +------------+------------------------------------------------------+ */
/* | 1000B | 8H | SW power down (analog + reference) | */
/* +------------+------------------------------------------------------+ */
/* | 1001B | 9H | Read CFR register data shown as SDO D(11–0) | */
/* +------------+------------------------------------------------------+ */
/* | 1010B | AH | Write CFR followed by 12-bit data. | */
/* +------------+------------------------------------------------------+ */
/* | 1011B | BH | Select test, voltage = (REFP+REFM)/2 | */
/* +------------+------------------------------------------------------+ */
/* | 1100B | CH | Select test, voltage = REFM | */
/* +------------+------------------------------------------------------+ */
/* | 1101B | DH | Select test, voltage = REFP | */
/* +------------+------------------------------------------------------+ */
/* | 1110B | EH | FIFO read, FIFO contents shown as SDO D(15–4) | */
/* +------------+------------------------------------------------------+ */
/******************************************************************************/
/* +------------+------------------------------------------------------+ */
/* | BIT | DEFININION | */
/* +------------+------------------------------------------------------+ */
/* | D11 | Reference select 0: External 1: internal | */
/* +------------+------------------------------------------------------+ */
/* | D10 | Internal reference voltage select | */
/* | | 0: Internal ref = 4 V 1: internal ref = 2 V | */
/* +------------+------------------------------------------------------+ */
/* | D9 | Sample period select | */
/* | | 0: Short sampling 12 SCLKs (1x sampling time) | */
/* | | 1: Long sampling 24 SCLKs (2x sampling time) | */
/* +------------+------------------------------------------------------+ */
/* | D(8-7) | Conversion clock source select | */
/* | | 00: Conversion clock = internal OSC | */
/* | | 01: Conversion clock = SCLK | */
/* | | 10: Conversion clock = SCLK/4 | */
/* | | 11: Conversion clock = SCLK/2 | */
/* +------------+------------------------------------------------------+ */
/* | D(6-5) | Conversion mode select | */
/* | | 00: Single shot mode [FIFO not used] | */
/* | | 01: Repeat mode | */
/* | | 10: Sweep mode | */
/* | | 11: Repeat sweep mode | */
/* +------------+------------------------------------------------------+ */
/* +------------+------------------------------------------------------+ */
/* | D(4-3) | Sweep auto sequence select | */
/* | | 00: N/A | */
/* | | 01: 0–1–2–3–0–1–2–3 | */
/* | | 10: 0–0–1–1–2–2–3–3 | */
/* | | 11: 0–1–0–1–0–1–0–1 | */
/* +------------+------------------------------------------------------+ */
/* | D2 | EOC/INT – pin function select | */
/* | | 0: Pin used as INT | */
/* | | 1: Pin used as EOC | */
/* +------------+------------------------------------------------------+ */
/* | D(1-0) | FIFO trigger level (sweep sequence length) | */
/* | | 00: Full (INT generated after FIFO level 7 filled) | */
/* | | 01: 3/4 (INT generated after FIFO level 5 filled) | */
/* | | 10: 1/2 (INT generated after FIFO level 3 filled) | */
/* | | 11: 1/4 (INT generated after FIFO level 1 filled) | */
/* +------------+------------------------------------------------------+ */
/******************************************************************************/
/* TLV2544 COMMAND */
/******************************************************************************/
#define ADC_CHANNEL0 0x0FFF
#define ADC_CHANNEL1 0x2FFF
#define ADC_CHANNEL2 0x4FFF
#define ADC_CHANNEL3 0x6FFF
#define ADC_POWERDOWN 0x8FFF
#define ADC_READCFR 0x9FFF
#define ADC_WRITECFR 0xA000
#define ADC_TESTAVERAGE 0xBFFF
#define ADC_TESTREFM 0xCFFF
#define ADC_TESTREFP 0xDFFF
#define ADC_FIFOREAD 0xEFFF
/******************************************************************************/
/* INIT CFR */
/******************************************************************************/
#define ADC_CFRINIT 0x0000
/******************************************************************************/
/* Reference select */
/******************************************************************************/
#define ADC_REFEXT 0x0000
#define ADC_REFINT 0x0800
/******************************************************************************/
/* Internal reference voltage select */
/******************************************************************************/
#define ADC_REF2V 0x0400
#define ADC_REF4V 0x0000
/******************************************************************************/
/* Sample period select */
/******************************************************************************/
#define ADC_LONGSAMPL 0x0200
#define ADC_SHORTSAMPL 0x0000
/******************************************************************************/
/* Conversion clock source select */
/******************************************************************************/
#define ADC_SCLK2 0x0180
#define ADC_SCLK4 0x0100
#define ADC_SCLK 0x0080
#define ADC_INTOSC 0x0000
/******************************************************************************/
/* Conversion mode select */
/******************************************************************************/
#define ADC_REPEADSWEEPMODE 0x0060
#define ADC_SWEEPMODE 0x0040
#define ADC_REPEADMODE 0x0020
#define ADC_SINGLEMODE 0x0000
/******************************************************************************/
/* Sweep auto sequence select */
/******************************************************************************/
#define ADC_SEQ01010101 0x0018
#define ADC_SEQ00112233 0x0010
#define ADC_SEQ01230123 0x0008
/******************************************************************************/
/* EOC/INT – pin function select */
/******************************************************************************/
#define ADC_EOC 0x0004
#define ADC_INIT 0x0000
/******************************************************************************/
/* FIFO trigger level (sweep sequence length) */
/******************************************************************************/
#define ADC_FIFO1_4INT 0x0060
#define ADC_FIFO1_2INT 0x0040
#define ADC_FIFO3_4INT 0x0020
#define ADC_FIFOFULLINT 0x0000
void Init_ADC(void);
void ADC_powerdown(void);
unsigned int read_ADCCFR(void);
unsigned int read_ADC(unsigned int cannel);
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