sfr22.h

嵌入式单片机开发,嵌入式单片机开发,嵌入式单片机开发

#define     ta0os       onsf0_addr.bit.b0      /* Timer A0 one-shot start flag */
#define     ta1os       onsf0_addr.bit.b1      /* Timer A1 one-shot start flag */
#define     ta2os       onsf0_addr.bit.b2      /* Timer A2 one-shot start flag */
#define     ta3os       onsf0_addr.bit.b3      /* Timer A3 one-shot start flag */
#define     ta4os       onsf0_addr.bit.b4      /* Timer A4 one-shot start flag */
#define     ta0tgl      onsf0_addr.bit.b6      /* Timer A0 event/trigger select bit */
#define     ta0tgh      onsf0_addr.bit.b7      /* Timer A0 event/trigger select bit */

/*------------------------------------------------------
    One-shot start flag 1
------------------------------------------------------*/
union byte_def onsf1_addr;
#define     onsf1       onsf1_addr.byte

#define     ta5os       onsf1_addr.bit.b0      /* Timer A5 one-shot start flag */
#define     ta6os       onsf1_addr.bit.b1      /* Timer A6 one-shot start flag */
#define     ta7os       onsf1_addr.bit.b2      /* Timer A7 one-shot start flag */
#define     ta5tgl      onsf1_addr.bit.b6      /* Timer A5 event/trigger select bit */
#define     ta5tgh      onsf1_addr.bit.b7      /* Timer A5 event/trigger select bit */

/*------------------------------------------------------
    Clock prescaler reset flag
------------------------------------------------------*/
union byte_def cpsrf_addr;
#define     cpsrf       cpsrf_addr.byte

#define     cpsr        cpsrf_addr.bit.b7      /* Clock prescaler reset flag */

/*------------------------------------------------------
    Trigger select register 0
------------------------------------------------------*/
union byte_def trgsr0_addr;
#define     trgsr0      trgsr0_addr.byte

#define     ta1tgl      trgsr0_addr.bit.b0     /* Timer A1 event/trigger select bit */
#define     ta1tgh      trgsr0_addr.bit.b1     /* Timer A1 event/trigger select bit */
#define     ta2tgl      trgsr0_addr.bit.b2     /* Timer A2 event/trigger select bit */
#define     ta2tgh      trgsr0_addr.bit.b3     /* Timer A2 event/trigger select bit */
#define     ta3tgl      trgsr0_addr.bit.b4     /* Timer A3 event/trigger select bit */
#define     ta3tgh      trgsr0_addr.bit.b5     /* Timer A3 event/trigger select bit */
#define     ta4tgl      trgsr0_addr.bit.b6     /* Timer A4 event/trigger select bit */
#define     ta4tgh      trgsr0_addr.bit.b7     /* Timer A4 event/trigger select bit */

/*------------------------------------------------------
    Trigger select register 1
------------------------------------------------------*/
union byte_def trgsr1_addr;
#define     trgsr1      trgsr1_addr.byte

#define     ta6tgl      trgsr1_addr.bit.b0     /* Timer A6 event/trigger select bit */
#define     ta6tgh      trgsr1_addr.bit.b1     /* Timer A6 event/trigger select bit */
#define     ta7tgl      trgsr1_addr.bit.b2     /* Timer A7 event/trigger select bit */
#define     ta7tgh      trgsr1_addr.bit.b3     /* Timer A7 event/trigger select bit */

/*------------------------------------------------------
    Up/down flag 0 (bit symbols delete)
------------------------------------------------------*/
/* union byte_def udf0_addr; */
/* #define     udf0        udf0_addr.byte */

/* #define     ta0ud       udf0_addr.bit.b0        /* Timer A0 up/down flag ; Remove 2000.6.21 */
/* #define     ta1ud       udf0_addr.bit.b1        /* Timer A1 up/down flag ; Remove 2000.6.21 */
/* #define     ta2ud       udf0_addr.bit.b2        /* Timer A2 up/down flag ; Remove 2000.6.21 */
/* #define     ta3ud       udf0_addr.bit.b3        /* Timer A3 up/down flag ; Remove 2000.6.21 */
/* #define     ta4ud       udf0_addr.bit.b4        /* Timer A4 up/down flag ; Remove 2000.6.21 */
/* #define     ta2p        udf0_addr.bit.b5        /* Timer A2 two-phase pulse signal processing select bit ; Remove 2000.6.21 */
/* #define     ta3p        udf0_addr.bit.b6        /* Timer A3 two-phase pulse signal processing select bit ; Remove 2000.6.21 */
/* #define     ta4p        udf0_addr.bit.b7        /* Timer A4 two-phase pulse signal processing select bit ; Remove 2000.6.21 */

/*------------------------------------------------------
    Up/down flag 1 (bit symbols delete)
------------------------------------------------------*/
/* union byte_def udf1_addr; */
/* #define     udf1        udf1_addr.byte */

/* #define     ta5ud       udf1_addr.bit.b0        /* Timer A5 up/down flag ; Remove 2000.6.21 */
/* #define     ta6ud       udf1_addr.bit.b1        /* Timer A6 up/down flag ; Remove 2000.6.21 */
/* #define     ta7ud       udf1_addr.bit.b2        /* Timer A7 up/down flag ; Remove 2000.6.21 */
/* #define     ta7p        udf1_addr.bit.b5        /* Timer A7 two-phase pulse signal processing select bit ; Remove 2000.6.21 */

/*------------------------------------------------------
    UART transmit/receive control register 2
------------------------------------------------------*/
union byte_def ucon_addr;
#define     ucon        ucon_addr.byte

#define     u0irs       ucon_addr.bit.b0    /* UART0 transmit interrupt cause select bit */
#define     u1irs       ucon_addr.bit.b1    /* UART1 transmit interrupt cause select bit */
#define     u0rrm       ucon_addr.bit.b2    /* UART0 continuous receive mode enable bit */
#define     u1rrm       ucon_addr.bit.b3    /* UART1 continuous receive mode enable bit */
#define     clkmd0      ucon_addr.bit.b4    /* CLK/CLKS select bit 0 */
#define     clkmd1      ucon_addr.bit.b5    /* CLK/CLKS select bit 1 */
/* #define     rcsp        ucon_addr.bit.b6    /* Separate CTS/RTS bit ; Remove 2000.6.21 */

/*------------------------------------------------------
    Flash memory control register ; modify 2000.6.21
------------------------------------------------------*/
union byte_def fmcr_addr;
#define     fmcr        fmcr_addr.byte

/* #define     fmcr0       fmcr_addr.bit.b0    /* RY/BY~ status bit */
/* #define     fmcr1       fmcr_addr.bit.b1    /* Flash entry bit */
/* #define     fmcr3       fmcr_addr.bit.b3    /* Flash reset bit */

#define     fmcr0       fmcr_addr.bit.b0    /* RY/BY~ status flag ; modify 2000.6.21 */
#define     fmcr1       fmcr_addr.bit.b1    /* CPU rewrite mode select bit ; modify 2000.6.21 */
#define     fmcr2       fmcr_addr.bit.b2    /* CPU rewrite mode entry flag ; modify 2000.6.21 */
#define     fmcr3       fmcr_addr.bit.b3    /* Flash momory reset bit ; modify 2000.6.21 */

/*------------------------------------------------------
    UART2 transmit/receive control register 1
------------------------------------------------------*/
union byte_def u2c1_addr;
#define     u2c1        u2c1_addr.byte
#define     te_u2c1     u2c1_addr.bit.b0    /* Transmit enable bit */
#define     ti_u2c1     u2c1_addr.bit.b1    /* Transmit buffer empty flag */
#define     re_u2c1     u2c1_addr.bit.b2    /* Receive enable bit */
#define     ri_u2c1     u2c1_addr.bit.b3    /* Receive complete flag */
#define     u2irs       u2c1_addr.bit.b4    /* UART2 transmit interrupt cause select bit */
#define     u2rrm       u2c1_addr.bit.b5    /* UART2 continuous receive mode enable bit */
#define     u2lch       u2c1_addr.bit.b6    /* Data logic select bit */
#define     u2ere       u2c1_addr.bit.b7    /* Error signal output enable bit */

/*------------------------------------------------------
    UART2 special mode register 2
------------------------------------------------------*/
union byte_def u2smr2_addr;
#define     u2smr2          u2smr2_addr.byte

#define     iicm2   u2smr2_addr.bit.b0      /* IIC mode selection bit 2*/
#define     csc     u2smr2_addr.bit.b1      /* Clock-synchronous bit */
#define     swc     u2smr2_addr.bit.b2      /* SCL wait output bit */
#define     als     u2smr2_addr.bit.b3      /* SDA output stop bit */
#define     stac    u2smr2_addr.bit.b4      /* UART2 initialization bit */
#define     swc2    u2smr2_addr.bit.b5      /* SCL wait output bit 2 */
#define     sdhi    u2smr2_addr.bit.b6      /* SDA output disable bit */
#define     shtc    u2smr2_addr.bit.b7      /* Start/stop condition control bit */

/*------------------------------------------------------
    UART2 special mode register
------------------------------------------------------*/
union byte_def u2smr_addr;
#define     u2smr   u2smr_addr.byte
#define     iicm    u2smr_addr.bit.b0       /* IIC mode select bit */
#define     abc     u2smr_addr.bit.b1       /* Arbitration lost detecting flag control bit */
#define     bbs     u2smr_addr.bit.b2       /* Bus busy flag */
#define     lsyn    u2smr_addr.bit.b3       /* SCLL sync output enable bit */
#define     abscs   u2smr_addr.bit.b4       /* Bus collision detect sampling clock select bit */
#define     acse    u2smr_addr.bit.b5       /* Auto clear function select bit of transmit enable bit */
#define     sss     u2smr_addr.bit.b6       /* Transmit start condition select bit */

/*------------------------------------------------------
    LCD mode register
------------------------------------------------------*/
union byte_def lcdm_addr;
#define     lcdm    lcdm_addr.byte
#define     lcdt0   lcdm_addr.bit.b0        /* Duty ratio select bit */
#define     lcdt1   lcdm_addr.bit.b1        /* Duty ratio select bit */
#define     bias    lcdm_addr.bit.b2        /* Bias control bit */
#define     lcden   lcdm_addr.bit.b3        /* LCD enable bit */
#define     pump    lcdm_addr.bit.b4        /* Voltage multiplier control bit */
#define     lramout lcdm_addr.bit.b5        /* LCDRAM output bit */
#define     lsrc    lcdm_addr.bit.b7        /* LCDCK count source select bit */

/*------------------------------------------------------
    Segment output enable register
------------------------------------------------------*/
union byte_def seg_addr;
#define     seg     seg_addr.byte
#define     sego0   seg_addr.bit.b0         /* Segment output enable bit 0 */
#define     sego1   seg_addr.bit.b1         /* Segment output enable bit 1 */
#define     sego2   seg_addr.bit.b2         /* Segment output enable bit 2 */
#define     sego3   seg_addr.bit.b3         /* Segment output enable bit 3 */
#define     sego4   seg_addr.bit.b4         /* Segment output enable bit 4 */
#define     sego5   seg_addr.bit.b5         /* Segment output enable bit 5 */
#define     sego6   seg_addr.bit.b6         /* Segment output enable bit 6 */
#define     sego7   seg_addr.bit.b7         /* LCD output enable bit */

/*------------------------------------------------------
    LCD frame frequency counter
------------------------------------------------------*/
union byte_def lcdtim_addr;
#define     lcdtim      lcdtim_addr.byte

/*------------------------------------------------------
    LCD RAM0
------------------------------------------------------*/
union byte_def lram0_addr;
#define     lram0       lram0_addr.byte
#define     com0_seg0   lram0_addr.bit.b0
#define     com1_seg0   lram0_addr.bit.b1
#define     com2_seg0   lram0_addr.bit.b2
#define     com3_seg0   lram0_addr.bit.b3
#define     com0_seg1   lram0_addr.bit.b4
#define     com1_seg1   lram0_addr.bit.b5
#define     com2_seg1   lram0_addr.bit.b6
#define     com3_seg1   lram0_addr.bit.b7

/*------------------------------------------------------
    LCD RAM1
------------------------------------------------------*/
union byte_def lram1_addr;
#define     lram1       lram1_addr.byte
#define     com0_seg2   lram1_addr.bit.b0
#define     com1_seg2   lram1_addr.bit.b1
#define     com2_seg2   lram1_addr.bit.b2
#define     com3_seg2   lram1_addr.bit.b3
#define     com0_seg3   lram1_addr.bit.b4
#define     com1_seg3   lram1_addr.bit.b5
#define     com2_seg3   lram1_addr.bit.b6
#define     com3_seg3   lram1_addr.bit.b7

/*------------------------------------------------------
    LCD RAM2
------------------------------------------------------*/
union byte_def lram2_addr;
#define     lram2       lram2_addr.byte
#define     com0_seg4   lram2_addr.bit.b0
#define     com1_seg4   lram2_addr.bit.b1
#define     com2_seg4   lram2_addr.bit.b2
#define     com3_seg4   lram2_addr.bit.b3
#define     com0_seg5   lram2_addr.bit.b4
#define     com1_seg5   lram2_addr.bit.b5
#define     com2_seg5   lram2_addr.bit.b6
#define     com3_seg5   lram2_addr.bit.b7

/*------------------------------------------------------
    LCD RAM3
------------------------------------------------------*/
union byte_def lram3_addr;
#define     lram3       lram3_addr.byte
#define     com0_seg6   lram3_addr.bit.b0
#define     com1_seg6   lram3_addr.bit.b1
#define     com2_seg6   lram3_addr.bit.b2
#define     com3_seg6   lram3_addr.bit.b3
#define     com0_seg7   lram3_addr.bit.b4
#define     com1_seg7   lram3_addr.bit.b5
#define     com2_seg7   lram3_addr.bit.b6
#define     com3_seg7   lram3_addr.bit.b7

/*------------------------------------------------------
    LCD RAM4
------------------------------------------------------*/
union byte_def lram4_addr;
#define     lram4       lram4_addr.byte
#define     com0_seg8   lram4_addr.bit.b0
#define     com1_seg8   lram4_addr.bit.b1
#define     com2_seg8   lram4_addr.bit.b2