📄 sfr22.h
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Up/down flag 1 ; Use "MOV" instruction when writing to this register. 2000.6.21 modify
--------------------------------------------------------*/
unsigned char udf1_addr; /* UP/down flag 1 */
#define udf1 udf1_addr
/*--------------------------------------------------------
Up/down flag 0 ; Use "MOV" instruction when writing to this register. 2000.6.21 modify
--------------------------------------------------------*/
unsigned char udf0_addr; /* UP/down flag 0 */
#define udf0 udf0_addr
/********************************************************
* declare SFR short *
********************************************************/
/*--------------------------------------------------------
Timer registers : Read and write data in 16-bit units. 2000.6.21 modify
--------------------------------------------------------*/
unsigned short ta5_addr; /* Timer A5 register */
#define ta5 ta5_addr
unsigned short ta6_addr; /* Timer A6 register */
#define ta6 ta6_addr
unsigned short ta7_addr; /* Timer A7 register */
#define ta7 ta7_addr
unsigned short tb3_addr; /* Timer B3 register */
#define tb3 tb3_addr
unsigned short tb4_addr; /* Timer B4 register */
#define tb4 tb4_addr
unsigned short tb5_addr; /* Timer B5 register */
#define tb5 tb5_addr
unsigned short ta0_addr; /* Timer A0 register */
#define ta0 ta0_addr
unsigned short ta1_addr; /* Timer A1 register */
#define ta1 ta1_addr
unsigned short ta2_addr; /* Timer A2 register */
#define ta2 ta2_addr
unsigned short ta3_addr; /* Timer A3 register */
#define ta3 ta3_addr
unsigned short ta4_addr; /* Timer A4 register */
#define ta4 ta4_addr
unsigned short tb0_addr; /* Timer B0 register */
#define tb0 tb0_addr
unsigned short tb1_addr; /* Timer B1 register */
#define tb1 tb1_addr
unsigned short tb2_addr; /* Timer B2 register */
#define tb2 tb2_addr
/********************************************************
* declare SFR bit *
********************************************************/
struct bit_def {
char b0:1;
char b1:1;
char b2:1;
char b3:1;
char b4:1;
char b5:1;
char b6:1;
char b7:1;
};
union byte_def{
struct bit_def bit;
char byte;
};
/*------------------------------------------------------
Clock divided counter control register
------------------------------------------------------*/
union byte_def cdcc_addr;
#define cdcc cdcc_addr.byte
#define cdcs cdcc_addr.bit.b7 /* Clock divided counter start flag */
/*------------------------------------------------------
Processor mode register 0
------------------------------------------------------*/
union byte_def pm0_addr;
#define pm0 pm0_addr.byte
#define pm00 pm0_addr.bit.b0 /* Processor mode bit */
#define pm01 pm0_addr.bit.b1 /* Processor mode bit */
/* #define pm02 pm0_addr.bit.b2 /* Reserved bit ; Remove 2000.6.21 */
#define pm03 pm0_addr.bit.b3 /* Software reset bit */
/*------------------------------------------------------
Processor mode register 1
------------------------------------------------------*/
union byte_def pm1_addr;
#define pm1 pm1_addr.byte
/* #define pm10 pm1_addr.bit.b0 /* Reserved bit ; Remove 2000.6.21 */
/* #define pm11 pm1_addr.bit.b1 /* Reserved bit ; Remove 2000.6.21 */
#define pm17 pm1_addr.bit.b7 /* Wait bit */
/*------------------------------------------------------
System clock control register 0
------------------------------------------------------*/
union byte_def cm0_addr;
#define cm0 cm0_addr.byte
#define cm00 cm0_addr.bit.b0 /* Clock output function select bit */
#define cm01 cm0_addr.bit.b1 /* Clock output function select bit */
#define cm02 cm0_addr.bit.b2 /* WAIT peripheral function clock stop bit */
#define cm03 cm0_addr.bit.b3 /* Xcin-Xcout drive capacity select bit */
#define cm04 cm0_addr.bit.b4 /* Sub clock (Xcin-Xcout) oscillation enable bit */
#define cm05 cm0_addr.bit.b5 /* Main clock stop bit */
#define cm06 cm0_addr.bit.b6 /* Main clock division select bit 0 */
#define cm07 cm0_addr.bit.b7 /* System clock select bit */
/*------------------------------------------------------
System clock control register 1
------------------------------------------------------*/
union byte_def cm1_addr;
#define cm1 cm1_addr.byte
#define cm10 cm1_addr.bit.b0 /* All clock stop control bit */
/* #define cm11 cm1_addr.bit.b1 /* Reserved bit ; Remove 2000.6.21 */
/* #define cm12 cm1_addr.bit.b2 /* Reserved bit ; Remove 2000.6.21 */
/* #define cm13 cm1_addr.bit.b3 /* Reserved bit ; Remove 2000.6.21 */
#define cm14 cm1_addr.bit.b4 /* fc132 clock select bit */
#define cm15 cm1_addr.bit.b5 /* Xin-Xout drive capacity select bit */
#define cm16 cm1_addr.bit.b6 /* Main clock division select bit 1 */
#define cm17 cm1_addr.bit.b7 /* Main clock division select bit 1 */
/*------------------------------------------------------
Address match interrupt enable register
------------------------------------------------------*/
union byte_def aier_addr;
#define aier aier_addr.byte
#define aier0 aier_addr.bit.b0 /* Address match interrupt 0 enable bit */
#define aier1 aier_addr.bit.b1 /* Address match interrupt 1 enable bit */
/*------------------------------------------------------
Protect register
------------------------------------------------------*/
union byte_def prcr_addr;
#define prcr prcr_addr.byte
#define prc0 prcr_addr.bit.b0 /* Enables writing to system clock control registers 0 and 1 */
#define prc1 prcr_addr.bit.b1 /* Enables writing to processor mode registers 0 and 1 */
/*------------------------------------------------------
Watchdog timer start register
------------------------------------------------------*/
union byte_def wdts_addr;
#define wdts wdts_addr.byte
/*------------------------------------------------------
Watchdog timer control register
------------------------------------------------------*/
union byte_def wdc_addr;
#define wdc wdc_addr.byte
/* #define wdc5 wdc_addr.bit.b5 /* Reserved bit ; Remove 2000.6.21 */
/* #define wdc6 wdc_addr.bit.b6 /* Reserved bit ; Remove 2000.6.21 */
#define wdc7 wdc_addr.bit.b7 /* Prescaler select bit */
/*------------------------------------------------------
Interrupt request cause select register 0
------------------------------------------------------*/
union byte_def ifsr0_addr;
#define ifsr0 ifsr0_addr.byte
#define ifsr00 ifsr0_addr.bit.b0 /* INT4~ input pin select bit */
#define ifsr01 ifsr0_addr.bit.b1 /* INT4~ input pin select bit */
#define ifsr02 ifsr0_addr.bit.b2 /* INT5~ input pin select bit */
#define ifsr03 ifsr0_addr.bit.b3 /* INT5~ input pin select bit */
#define ifsr04 ifsr0_addr.bit.b4 /* Interrupt request cause select bit */
/* #define ifsr05 ifsr0_addr.bit.b5 /* Reserved bit ; Remove 2000.6.21 */
/* #define ifsr06 ifsr0_addr.bit.b6 /* Reserved bit ; Remove 2000.6.21 */
/*------------------------------------------------------
Interrupt request cause select register 1
------------------------------------------------------*/
union byte_def ifsr1_addr;
#define ifsr1 ifsr1_addr.byte
#define ifsr10 ifsr1_addr.bit.b0 /* INT0~ interrupt polarity switching bit */
#define ifsr11 ifsr1_addr.bit.b1 /* INT1~ interrupt polarity switching bit */
#define ifsr12 ifsr1_addr.bit.b2 /* INT2~ interrupt polarity switching bit */
#define ifsr13 ifsr1_addr.bit.b3 /* INT3~ interrupt polarity switching bit */
#define ifsr14 ifsr1_addr.bit.b4 /* INT4~ interrupt polarity switching bit */
#define ifsr15 ifsr1_addr.bit.b5 /* INT5~ interrupt polarity switching bit */
#define ifsr16 ifsr1_addr.bit.b6 /* Interrupt request cause select bit */
#define ifsr17 ifsr1_addr.bit.b7 /* Interrupt request cause select bit */
/*------------------------------------------------------
Real time port control register
------------------------------------------------------*/
union byte_def rtp_addr;
#define rtp rtp_addr.byte
#define rtp0 rtp_addr.bit.b0 /* P00 to P03 real time port mode select bit */
#define rtp1 rtp_addr.bit.b1 /* P04 to P07 real time port mode select bit */
#define rtp2 rtp_addr.bit.b2 /* P10 to P13 real time port mode select bit */
#define rtp3 rtp_addr.bit.b3 /* P14 to P17 real time port mode select bit */
#define rtp4 rtp_addr.bit.b4 /* P20 to P23 real time port mode select bit */
#define rtp5 rtp_addr.bit.b5 /* P24 to P27 real time port mode select bit */
#define rtp6 rtp_addr.bit.b6 /* P120 to P123 real time port mode select bit */
#define rtp7 rtp_addr.bit.b7 /* P124 to P127 real time port mode select bit */
/*------------------------------------------------------
Count start flag 0
------------------------------------------------------*/
union byte_def tabsr0_addr;
#define tabsr0 tabsr0_addr.byte
#define ta0s tabsr0_addr.bit.b0 /* Timer A0 count start flag */
#define ta1s tabsr0_addr.bit.b1 /* Timer A1 count start flag */
#define ta2s tabsr0_addr.bit.b2 /* Timer A2 count start flag */
#define ta3s tabsr0_addr.bit.b3 /* Timer A3 count start flag */
#define ta4s tabsr0_addr.bit.b4 /* Timer A4 count start flag */
#define tb0s tabsr0_addr.bit.b5 /* Timer B0 count start flag */
#define tb1s tabsr0_addr.bit.b6 /* Timer B1 count start flag */
#define tb2s tabsr0_addr.bit.b7 /* Timer B2 count start flag */
/*------------------------------------------------------
Count start flag 1
------------------------------------------------------*/
union byte_def tabsr1_addr;
#define tabsr1 tabsr1_addr.byte
#define ta5s tabsr1_addr.bit.b0 /* Timer A5 count start flag */
#define ta6s tabsr1_addr.bit.b1 /* Timer A6 count start flag */
#define ta7s tabsr1_addr.bit.b2 /* Timer A7 count start flag */
#define tb3s tabsr1_addr.bit.b5 /* Timer B3 count start flag */
#define tb4s tabsr1_addr.bit.b6 /* Timer B4 count start flag */
#define tb5s tabsr1_addr.bit.b7 /* Timer B5 count start flag */
/*------------------------------------------------------
One-shot start flag 0
------------------------------------------------------*/
union byte_def onsf0_addr;
#define onsf0 onsf0_addr.byte
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