class.ptf

周立功 SOPC嵌入式系统实验教程 网卡芯片驱动及其应用

#:-:
#:-: file: class.ptf
#:-: date: 2005.12.7 16:19:57
#:-:
#:-: Author: zhoushuwu
#:-: Guangzhou ZHIYUAN ELECTRONIC CO.,LTD.Research centre
#:-: http://www.zyinside.com, http://www.zlgmcu.com
#:-:
# This is a hardware interface to an exteral RTL8019 10M
# Ethernet PHY/MAC.
# 
# This adds an avalon_tristate-type slave to your system, representing
# the bus-interface to the external device.
# 
# In the past, this component "came with" the plugs networking
# library.  No more.  Now this component "comes with" a minimal API
# that makes it visible to plugs, but plugs is delivered separately
# as a software component.
# 
   CLASS zlg_avalon_rtl8019
   {
     
      USER_INTERFACE 
      {
         USER_LABELS 
         {
            name = "RTL8019 Interface (Ethernet)";
            description = "Interface to external 10Mb MAC/PHY chip: SMSC RTL8019";
            technology = "SmartSOPC,Ethernet";
            license = "full";
         }
         
         WIZARD_UI default
         {
            title = "Ethernet Adapter - {{ $MOD }}";
            CONTEXT 
            {
               SPW = "SLAVE s1/PORT_WIRING";
               CONSTANTS = "WIZARD_SCRIPT_ARGUMENTS/CONSTANTS";
               SBI = "SLAVE s1/SYSTEM_BUILDER_INFO";
            }
            GROUP 
            {
               align = "left";
               title = "Presets";
               RADIO 
               {
                  id = "devboard";
                  title = "RTL8019 MAC/PHY On Development Board";
                  font = "bold";
                  key = "b";
                  GROUP 
                  {
                     indent = "30";
                     TEXT 
                     {
                        title = "
Registers are aligned on half-word boundaries. <BR>
The full 6-bit address width of the chip is used. <BR>";
                        font = "small";
                     }
                  }
                  DATA 
                  {
#                     $SPW/PORT byteenablen/width = "2";
                     $SPW/PORT address/width = "6";
                     $SPW/PORT data/width = "16";
                     $SBI/Data_Width = "16";
                     $SBI/Address_Width = "6";
                     $CONSTANTS/CONSTANT RTL8019_DATA_BUS_WIDTH/value = "16";
                  }
               }
            }
         }
      }
      ASSOCIATED_FILES 
      {
         Add_Program = "default"; # No generator program, because this is a system-external component:
         Generator_Program = "--none--";
         Edit_Program = "default";
      }
      MODULE_DEFAULTS 
      {
         class = "zlg_avalon_rtl8019";
         class_version = "1.0";
         WIZARD_SCRIPT_ARGUMENTS 
         {
            Is_Ethernet_Mac = "1";
            CONSTANTS 
            {
               CONSTANT RTL8019_DATA_BUS_WIDTH
               {
                  value = "16";
                  comment = "width 16, depending on data bus wiring";
               }
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Instantiate_In_System_Module = "0";
            Wire_Test_Bench_Values = "1";
            Is_Enabled = "1";
            Top_Level_Ports_Are_Enumerated = "1";
         }
         SLAVE s1
         {
            SYSTEM_BUILDER_INFO 
            {
               Instantiate_In_System_Module = "0";
               Is_Enabled = "1";
               Is_Bus_Master = "0";
               Bus_Type = "avalon_tristate";
               Uses_Tri_State_Data_Bus = "1";
               Address_Alignment = "native";
               Address_Width = "6";
               Data_Width = "16";
               Has_IRQ = "0";
               Read_Wait_States = "200ns";
               Write_Wait_States = "200ns";
               Setup_Time = "50ns";
               Hold_Time = "50ns";
               Is_Memory_Device = "0";
               Date_Modified = "2005.12.7.10:51:51";
               IRQ_Number = "--unknown--";
               Base_Address = "--unknown--";
               Tri_State_Data_Bus = "--unknown--";
            }
            PORT_WIRING 
            {
#               PORT irq
#              {
#                  direction = "output";
#                  width = "1";
#                  type = "irq";
#                  test_bench_value = "0";
#               }
#               PORT byteenablen
#               {
#                  is_shared = "1";
#                  direction = "input";
#                  width = "4";
#                  type = "byteenable_n";
#               }
               PORT select_n
        {
          width = "1";
          is_shared = "0";
          direction = "input";
          type = "chipselect_n";
        }
               PORT address
               {
                  is_shared = "1";
                  direction = "input";
                  width = "8";
                  type = "address";
               }
               PORT data
               {
                  is_shared = "1";
                  direction = "inout";
                  width = "16";
                  type = "data";
               }
               PORT write_n
               {
                  direction = "input";
                  width = "1";
                  is_shared = "1";
                  type = "write_n";
               }
               PORT read_n
               {
                  direction = "input";
                  width = "1";
                  is_shared = "1";
                  type = "read_n";
               }
#               PORT reset
#               {
#                  direction = "input";
#                 width = "1";
#                  type = "reset";
#               }
	       # this disables previous example design ports having reset_n port
#               PORT reset_n
#               {
#                  direction = "input";
#                  width = "1";
#                  type = "reset_n";
#                  Is_Enabled = "0";
#               }
#	       PORT ardy
#               {
#                  direction = "output";
#                  width     = "1";
#                  type      = "inhibitrequest_n";
#                  Is_Enabled = "0";
#               }
            }
         }
      }
   }