utils.doc

一些网络上用到的知识

   fname.target_extension:fname.source_extension
     [command]
     [command]
     ...

for any fname.

Implicit rules are used if no explicit rule for a given target can be found
or if an explicit rule with no commands exists for the target.

The extension of the file name in question is used to determine which
implicit rule to use. The implicit rule is applied if a file is found with
the same name as the target, but with the mentioned source extension. For
example, suppose you had a makefile (named MAKEFILE) whose contents were

   .asm.obj:
     tasm $*.asm,$*.obj;

If you had an assembly language routine named RATIO.ASM that you wanted to
compile to RATIO.OBJ, you could use the command

   make ratio.obj

MAKE would take RATIO.OBJ to be the target and create it by executing the
command:

   tasm ratio.asm,ratio.obj;

Implicit rules are also used if an explicit rule is given with no commands.
Suppose, as mentioned before, you had the following implicit rule at the
start of your makefile:

   .pas.tpu:
     tpc $<

You could then rewrite some explicit rules as follows:

   myglobal.tpu: myglobal.pas
   myutils.tpu: myutils.pas myglobal.tpu myutil.obj

Since you don't have explicit information on how to create these .TPU
files, MAKE applies the implicit rule defined earlier.

Several implicit rules can be written with the same target extension, but
only one such rule can apply at a time. If more than one implicit rule
exists for a given target extension, each rule is checked in the order the
rules appear in the makefile, until all applicable rules are checked.

MAKE uses the first implicit rule that it discovers for a file with the
source extension. Even if the commands of that rule fail, no more implicit
rules are checked.

All lines following an implicit rule are considered to be part of the
command list for the rule, up to the next line that begins without
whitespace or to the end of the file. Blank lines are ignored. The syntax
for a command line is provided later in this appendix.

MAKE does not know the full file name with an implicit rule, as it does
with explicit rules. For that reason, special macros are provided with MAKE
that allow you to include the name of the file being built by the rule.


 Command Lists
---------------

Commands in a command list must be indented--that is, preceded by at least
one space character or tab--and take the form

   [ prefix ... ] command_body

Each command line in a command list consists of an (optional) list of
prefixes, followed by a single command body.

The prefixes allowed in a command modify the treatment of these commands by
MAKE. The prefix is either the at (@) sign or a hyphen (-) followed
immediately by a number.

   @   Keeps MAKE from displaying the command before executing it. The
       display is hidden even if the -s option was not given on the MAKE
       command line. This prefix applies only to the command on which it
       appears.

   -num   Affects how MAKE treats exit codes. If a number (num) is
          provided, then MAKE will abort processing only if the exit status
          exceeds the number given. In this example, MAKE will abort only
          if the exit status exceeds 4:

             -4 myprog sample.x

          If no -num prefix is given, MAKE checks the exit status for the
          command. If the status is nonzero, MAKE will stop and delete the
          current target file.

   -   With a hyphen but no number, MAKE will not check the exit status at
       all. Regardless of what the exit status was, MAKE will continue.

The command body is treated exactly as if it were entered as a line to
COMMAND.COM, with the exception that redirection and pipes are not
supported. MAKE executes the following built-in commands by invoking a copy
of COMMAND.COM to perform them:

   BREAK      CD      CHDIR      CLS      COPY
   MD         MKDIR   PATH       PROMPT   REN
   RENAME     SET     TIME       TYPE     VER
   VERIFY     VOL

MAKE searches for any other command name using the MS-DOS search algorithm:

   o The current directory is searched first, followed by each directory
     in the path.

   o In each directory, first a file with the extension .COM is checked,
     then an .EXE file, and finally a .BAT.

   o If a .BAT file is found, a copy of COMMAND.COM is invoked to execute
     the batch file.


This command will cause MYPROG.PAS to be searched for, using the full
search algorithm:

   tpc myprog.pas /$B+,R+,I+


 Macros
--------

Often certain commands, file names, or options are used again and again in
your makefile. In an example earlier in this appendix, all the TPC commands
used the switch /Tc:\tp5\bin, which means that the files TPC.CFG and
TURBO.TPL are in the subdirectory C:\TP5\BIN. Suppose you wanted to switch
to another subdirectory for those files; what would you do? You could go
through and modify all the /T options, inserting the appropriate path name.
Or, you could define a macro.

A macro is a name that represents some string of characters (letters and
digits). A macro definition gives a macro name and the expansion text;
thereafter, when MAKE encounters the macro name, it replaces the name with
the expansion text.

Suppose you defined the following macro at the start of your makefile:

   TURBO=c:\tp5\bin

You've defined the macro TURBO, which is equivalent to the string
c:\tp5\bin. You could now rewrite the makefile as follows:

   TURBO=c:\tp5\bin
   myapp.exe:  myapp.pas myglobal.tpu myutils.tpu
     tpc myapp /T$(TURBO)

   myutils.tpu: myutils.pas myglobal.tpu myutil.obj
     tpc myutils /T$(TURBO)


Everywhere the Turbo directory is specified, you use the macro invocation
$(TURBO). When you run MAKE, $(TURBO) is replaced with its expansion text,
c:\TP5.BIN. The result is the same set of commands you had before but with
greater flexibility.

In fact, if you leave out the first line altogether, you can specify which 
subdirectory you want each time you run MAKE, using the -D (Define) option:

   make -DTURBO=c:\tp5\project

Macro definitions take the form

   macro_name=expansion text

where macro_name is the name of a macro made up of a string of letters and
digits with no whitespace in it, though you can have whitespace between
macro_name and the equal sign (=). [expansion text] is any arbitrary string
containing letters, digits, whitespace, and punctuation; it is ended by a
carriage return.  Note that macros are case sensitive.  Thus the macro
names Turbo, turbo and TURBO are all different.

If macro_name has previously been defined, either by a macro definition in
the makefile or by the -D option on the MAKE command line, the new
definition replaces the old.

Macros are invoked in your makefile with the format

   $(macro_name)

Macros in macros: Macros cannot be invoked on the left (macro_name) side of
a macro definition. They can be used on the right (expansion text) side,
but they are not expanded until the macro being defined is invoked. In
other words, when a macro invocation is expanded, any macros embedded in
its expansion text are also expanded.

MAKE comes with several special predefined macros built-in: $d, $*, $<, $:,
$., and $&. The first is a defined test macro, used in the conditional
directives !if and !elif; the others are file name macros, used in explicit
and implicit rules. The various file name macros work in similar ways,
expanding to some variation of the full path name of the file being built.
In addition, the current SET environment strings are automatically loaded
as macros, and the macro __MAKE__ is defined to be 1 (one).


 Defined Test Macro ($d)

This macro expands to 1 if the given macro name is defined, or to 0 if it
is not. The content of the macro's expansion text does not matter. This
special macro is allowed only in !if and !elif directives. For example, if
you wanted to modify your makefile so that it would use a particular Turbo
Pascal directory if you didn't specify one, you could put this at the start
of your makefile:

   !if !$d(TURBO)            # if TURBO is not defined
   TURBO=c:\tp5\bin          # define it to C:\TP5\BIN
   !endif

If you invoke MAKE with the command line

   make -DTURBO=c:\tp5\project

then TURBO is defined as c:\tp5\project. If, however, you just invoke MAKE
by itself,

   make

then TURBO is defined as c:\tp5\bin, your "default" subdirectory.


 Base File Name Macro ($*)

This macro is allowed in the commands for an explicit or an implicit rule.
The macro expands to the file name being built, excluding any extension,
like this:

   File name is A:\P\TESTFILE.PAS
   $* expands to A:\P\TESTFILE

For example, you could modify the explicit MYAPP.EXE rule already given to
look like this:

   myapp.exe:  myapp.pas myglobal.tpu myutils.tpu
     tpc $* /T$(TURBO)


 Full File Name Macro ($<)

The full file name macro ($<) is also used in the commands for an explicit
or implicit rule. In an explicit rule, $< expands to the full target file
name (including extension), like this:

   File name is A:\P\TESTFILE.PAS
   $< expands to A:\P\TESTFILE.PAS

In an implicit rule, $< takes on the file name plus the source extension.
For example, the previous implicit rule

   .asm.obj:
     tasm $*.asm,$*.obj;

can be rewritten as

   .asm.obj:
      tasm $<,$*.obj;


 File Name Path Macro ($:)

This macro expands to the path name (without the file name), like this:

   File name is A:\P\TESTFILE.PAS
   $: expands to A:\P\


 File Name and Extension Macro ($.)

This macro expands to the file name, with extension, like this:

   File name is A:\P\TESTFILE.PAS
   $. expands to TESTFILE.PAS


 File Name Only Macro ($&)

This macro expands to the file name only, without path or extension, like
this:

   File name is A:\P\TESTFILE.PAS
   $& expands to TESTFILE


 Directives
------------

The version of MAKE bundled with Turbo Pascal allows something that other
versions of MAKE don't: conditional directives similiar to those allowed
for Turbo Pascal. You can use these directives to include other makefiles,
to make the rules and commands conditional, to print out error messages,
and to "undefine" macros.

Directives in a makefile begin with an exclamation point (!). Here is the
complete list of MAKE directives:

   !include
   !if
   !else
   !elif
   !endif
   !error
   !undef

A file-inclusion directive (!include) specifies a file to be included into
the makefile for interpretation at the point of the directive. It takes the
following form:

   !include "filename"

or

   !include <filename>

These directives can be nested arbitrarily deep. If an include directive
attempts to include a file that has already been included in some outer
level of nesting (so that a nesting loop is about to start), the inner
include directive is rejected as an error.

Conditional directives (!if, !elif, !else, and !endif) give a programmer a