xianshi.rpt

EDA条件下乘法器的实现。AHDL语言实现输入显示乘法等功能

        | | | | | | | +------------- LC26 gc1
        | | | | | | | | +----------- LC32 gc2
        | | | | | | | | | +--------- LC27 gc3
        | | | | | | | | | | +------- LC28 gc4
        | | | | | | | | | | | +----- LC29 gc5
        | | | | | | | | | | | | +--- LC30 gc6
        | | | | | | | | | | | | | +- LC31 gc7
        | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | | | | | | A B |     Logic cells that feed LAB 'B':

Pin
44   -> - - - - - - - - - - - - - - | * - | <-- a1
11   -> * * * * * * * - - - - - - * | - * | <-- b1
9    -> * * * * * * * - - - - - - * | - * | <-- b2
8    -> * * * * * * * - - - - - - * | - * | <-- b3
6    -> * * * * * * * - - - - - - * | - * | <-- b4
43   -> - - - - - - - - - - - - - * | - * | <-- si


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                          c:\baowenlei\xianshi.rpt
xianshi

** EQUATIONS **

a1       : INPUT;
a2       : INPUT;
a3       : INPUT;
a4       : INPUT;
b1       : INPUT;
b2       : INPUT;
b3       : INPUT;
b4       : INPUT;
si       : INPUT;

-- Node name is 'ga1' 
-- Equation name is 'ga1', location is LC013, type is output.
 ga1     = LCELL( _EQ001 $  GND);
  _EQ001 =  a1 &  a2 & !a3 &  a4
         #  a1 & !a2 &  a3 &  a4
         #  a1 & !a2 & !a3 & !a4
         # !a1 & !a2 &  a3 & !a4;

-- Node name is 'ga2' 
-- Equation name is 'ga2', location is LC015, type is output.
 ga2     = LCELL( _EQ002 $  GND);
  _EQ002 =  a1 & !a2 &  a3 & !a4
         # !a1 & !a2 &  a3 &  a4
         #  a1 &  a2 &  a4
         # !a1 &  a2 &  a3;

-- Node name is 'ga3' 
-- Equation name is 'ga3', location is LC001, type is output.
 ga3     = LCELL( _EQ003 $  GND);
  _EQ003 =  a1 &  a2 &  a3 &  a4
         # !a1 &  a2 & !a3 & !a4
         # !a1 &  a3 &  a4;

-- Node name is 'ga4' 
-- Equation name is 'ga4', location is LC012, type is output.
 ga4     = LCELL( _EQ004 $  GND);
  _EQ004 = !a1 &  a2 & !a3 &  a4
         # !a1 & !a2 &  a3 & !a4
         #  a1 &  a2 &  a3
         #  a1 & !a2 & !a3;

-- Node name is 'ga5' 
-- Equation name is 'ga5', location is LC014, type is output.
 ga5     = LCELL( _EQ005 $  GND);
  _EQ005 = !a1 &  a2 & !a3 &  a4
         #  a1 & !a2 & !a3
         # !a2 &  a3 & !a4
         #  a1 & !a4;

-- Node name is 'ga6' 
-- Equation name is 'ga6', location is LC002, type is output.
 ga6     = LCELL( _EQ006 $  GND);
  _EQ006 =  a1 &  a2 &  a3 & !a4
         #  a1 & !a2 &  a3 &  a4
         # !a1 &  a2 & !a3 & !a4
         #  a1 & !a3 & !a4;

-- Node name is 'ga7' 
-- Equation name is 'ga7', location is LC016, type is output.
 ga7     = LCELL( _EQ007 $  GND);
  _EQ007 =  a1 &  a2 &  a3 & !a4
         # !a1 & !a2 &  a3 &  a4
         # !a2 & !a3 & !a4;

-- Node name is 'gb1' 
-- Equation name is 'gb1', location is LC021, type is output.
 gb1     = LCELL( _EQ008 $  GND);
  _EQ008 =  b1 &  b2 & !b3 &  b4
         #  b1 & !b2 &  b3 &  b4
         # !b1 & !b2 &  b3 & !b4
         # !b2 & !b3 & !b4;

-- Node name is 'gb2' 
-- Equation name is 'gb2', location is LC019, type is output.
 gb2     = LCELL( _EQ009 $ !b1);
  _EQ009 =  b1 &  b2 &  b4
         # !b2 &  b3 & !b4
         # !b1 &  b2 & !b3
         # !b1 & !b3 &  b4;

-- Node name is 'gb3' 
-- Equation name is 'gb3', location is LC017, type is output.
 gb3     = LCELL( _EQ010 $  GND);
  _EQ010 =  b2 &  b3 &  b4
         # !b1 &  b3 &  b4
         # !b1 & !b3 & !b4;

-- Node name is 'gb4' 
-- Equation name is 'gb4', location is LC018, type is output.
 gb4     = LCELL( _EQ011 $ !b2);
  _EQ011 = !b1 &  b2 & !b3 &  b4
         # !b1 & !b2 &  b4
         #  b1 &  b3;

-- Node name is 'gb5' 
-- Equation name is 'gb5', location is LC022, type is output.
 gb5     = LCELL( _EQ012 $ !b4);
  _EQ012 =  b1 & !b2 & !b3 &  b4
         # !b1 &  b2 & !b4;

-- Node name is 'gb6' 
-- Equation name is 'gb6', location is LC023, type is output.
 gb6     = LCELL( _EQ013 $  GND);
  _EQ013 =  b1 & !b2 &  b3 &  b4
         #  b1 &  b2 & !b4
         # !b3 & !b4;

-- Node name is 'gb7' 
-- Equation name is 'gb7', location is LC024, type is output.
 gb7     = LCELL( _EQ014 $  GND);
  _EQ014 =  b1 &  b2 &  b3 & !b4
         # !b1 & !b2 &  b3 &  b4
         # !b2 & !b3 & !b4;

-- Node name is 'gc1' 
-- Equation name is 'gc1', location is LC026, type is output.
 gc1     = LCELL( GND $  VCC);

-- Node name is 'gc2' 
-- Equation name is 'gc2', location is LC032, type is output.
 gc2     = LCELL( GND $  VCC);

-- Node name is 'gc3' 
-- Equation name is 'gc3', location is LC027, type is output.
 gc3     = LCELL( GND $  VCC);

-- Node name is 'gc4' 
-- Equation name is 'gc4', location is LC028, type is output.
 gc4     = LCELL( GND $  VCC);

-- Node name is 'gc5' 
-- Equation name is 'gc5', location is LC029, type is output.
 gc5     = LCELL( GND $  VCC);

-- Node name is 'gc6' 
-- Equation name is 'gc6', location is LC030, type is output.
 gc6     = LCELL( GND $  VCC);

-- Node name is 'gc7' 
-- Equation name is 'gc7', location is LC031, type is output.
 gc7     = LCELL( _EQ015 $ !si);
  _EQ015 = !b1 & !b2 & !b3 & !b4 &  si;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                   c:\baowenlei\xianshi.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 4,115K