📄 xianshi.rpt
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Project Information c:\baowenlei\xianshi.rpt
MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 04/10/2009 15:36:30
Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
Untitled
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
xianshi EPM7032SLC44-5 9 21 0 21 0 65 %
User Pins: 9 21 0
Project Information c:\baowenlei\xianshi.rpt
** PROJECT COMPILATION MESSAGES **
Warning: Primitive 'gc6' is stuck at VCC
Warning: Primitive 'gc5' is stuck at VCC
Warning: Primitive 'gc4' is stuck at VCC
Warning: Primitive 'gc3' is stuck at VCC
Warning: Primitive 'gc2' is stuck at VCC
Warning: Primitive 'gc1' is stuck at VCC
Device-Specific Information: c:\baowenlei\xianshi.rpt
xianshi
***** Logic for device 'xianshi' compiled without errors.
Device: EPM7032SLC44-5
Device Options:
Turbo Bit = ON
Security Bit = OFF
Enable JTAG Support = ON
User Code = ffff
Device-Specific Information: c:\baowenlei\xianshi.rpt
xianshi
** ERROR SUMMARY **
Info: Chip 'xianshi' in device 'EPM7032SLC44-5' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
g g V G G G g g
b a a C N N a s N b b
4 6 3 C D D 1 i D 3 4
-----------------------------------_
/ 6 5 4 3 2 1 44 43 42 41 40 |
#TDI | 7 39 | gb2
b3 | 8 38 | #TDO
b2 | 9 37 | gb1
GND | 10 36 | gb5
b1 | 11 35 | VCC
a4 | 12 EPM7032SLC44-5 34 | gb6
#TMS | 13 33 | gb7
a3 | 14 32 | #TCK
VCC | 15 31 | gc1
a2 | 16 30 | GND
ga4 | 17 29 | gc3
|_ 18 19 20 21 22 23 24 25 26 27 28 _|
------------------------------------
g g g g G V g g g g g
a a a a N C c c c c c
1 5 2 7 D C 2 7 6 5 4
N.C. = No Connect. This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: c:\baowenlei\xianshi.rpt
xianshi
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 7/16( 43%) 16/16(100%) 0/16( 0%) 4/36( 11%)
B: LC17 - LC32 14/16( 87%) 16/16(100%) 1/16( 6%) 5/36( 13%)
Total dedicated input pins used: 2/4 ( 50%)
Total I/O pins used: 32/32 (100%)
Total logic cells used: 21/32 ( 65%)
Total shareable expanders used: 0/32 ( 0%)
Total Turbo logic cells used: 21/32 ( 65%)
Total shareable expanders not available (n/a): 1/32 ( 3%)
Average fan-in: 2.90
Total fan-in: 61
Total input pins required: 9
Total fast input logic cells required: 0
Total output pins required: 21
Total bidirectional pins required: 0
Total reserved pins required 4
Total logic cells required: 21
Total flipflops required: 0
Total product terms required: 59
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 0
Synthesized logic cells: 0/ 32 ( 0%)
Device-Specific Information: c:\baowenlei\xianshi.rpt
xianshi
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
44 - - INPUT 0 0 0 0 0 7 0 a1
16 (11) (A) INPUT 0 0 0 0 0 7 0 a2
14 (10) (A) INPUT 0 0 0 0 0 7 0 a3
12 (8) (A) INPUT 0 0 0 0 0 7 0 a4
11 (7) (A) INPUT 0 0 0 0 0 8 0 b1
9 (6) (A) INPUT 0 0 0 0 0 8 0 b2
8 (5) (A) INPUT 0 0 0 0 0 8 0 b3
6 (3) (A) INPUT 0 0 0 0 0 8 0 b4
43 - - INPUT 0 0 0 0 0 1 0 si
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: c:\baowenlei\xianshi.rpt
xianshi
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
18 13 A OUTPUT t 0 0 0 4 0 0 0 ga1
20 15 A OUTPUT t 0 0 0 4 0 0 0 ga2
4 1 A OUTPUT t 0 0 0 4 0 0 0 ga3
17 12 A OUTPUT t 0 0 0 4 0 0 0 ga4
19 14 A OUTPUT t 0 0 0 4 0 0 0 ga5
5 2 A OUTPUT t 0 0 0 4 0 0 0 ga6
21 16 A OUTPUT t 0 0 0 4 0 0 0 ga7
37 21 B OUTPUT t 0 0 0 4 0 0 0 gb1
39 19 B OUTPUT t 1 0 1 4 0 0 0 gb2
41 17 B OUTPUT t 0 0 0 4 0 0 0 gb3
40 18 B OUTPUT t 0 0 0 4 0 0 0 gb4
36 22 B OUTPUT t 0 0 0 4 0 0 0 gb5
34 23 B OUTPUT t 0 0 0 4 0 0 0 gb6
33 24 B OUTPUT t 0 0 0 4 0 0 0 gb7
31 26 B OUTPUT t 0 0 0 0 0 0 0 gc1
24 32 B OUTPUT t 0 0 0 0 0 0 0 gc2
29 27 B OUTPUT t 0 0 0 0 0 0 0 gc3
28 28 B OUTPUT t 0 0 0 0 0 0 0 gc4
27 29 B OUTPUT t 0 0 0 0 0 0 0 gc5
26 30 B OUTPUT t 0 0 0 0 0 0 0 gc6
25 31 B OUTPUT t 0 0 0 5 0 0 0 gc7
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: c:\baowenlei\xianshi.rpt
xianshi
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+------------- LC13 ga1
| +----------- LC15 ga2
| | +--------- LC1 ga3
| | | +------- LC12 ga4
| | | | +----- LC14 ga5
| | | | | +--- LC2 ga6
| | | | | | +- LC16 ga7
| | | | | | |
| | | | | | | Other LABs fed by signals
| | | | | | | that feed LAB 'A'
LC | | | | | | | | A B | Logic cells that feed LAB 'A':
Pin
44 -> * * * * * * * | * - | <-- a1
16 -> * * * * * * * | * - | <-- a2
14 -> * * * * * * * | * - | <-- a3
12 -> * * * * * * * | * - | <-- a4
43 -> - - - - - - - | - * | <-- si
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: c:\baowenlei\xianshi.rpt
xianshi
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+--------------------------- LC21 gb1
| +------------------------- LC19 gb2
| | +----------------------- LC17 gb3
| | | +--------------------- LC18 gb4
| | | | +------------------- LC22 gb5
| | | | | +----------------- LC23 gb6
| | | | | | +--------------- LC24 gb7
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