📄 shuru.rpt
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* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: c:\baowenlei\shuru.rpt
shuru
** EQUATIONS **
A0 : INPUT;
A1 : INPUT;
A2 : INPUT;
A3 : INPUT;
A4 : INPUT;
LOA : INPUT;
LOB : INPUT;
-- Node name is 'ABLE'
-- Equation name is 'ABLE', location is LC032, type is output.
ABLE = LCELL( _EQ001 $ GND);
_EQ001 = LOA & !LOB;
-- Node name is 'C0'
-- Equation name is 'C0', location is LC026, type is output.
C0 = LCELL( _EQ002 $ GND);
_EQ002 = FF5 & !LOA & LOB
# FF5 & LOA & !LOB;
-- Node name is 'C1'
-- Equation name is 'C1', location is LC027, type is output.
C1 = LCELL( _EQ003 $ GND);
_EQ003 = FF6 & !LOA & LOB
# FF6 & LOA & !LOB;
-- Node name is 'C2'
-- Equation name is 'C2', location is LC028, type is output.
C2 = LCELL( _EQ004 $ GND);
_EQ004 = FF7 & !LOA & LOB
# FF7 & LOA & !LOB;
-- Node name is 'C3'
-- Equation name is 'C3', location is LC010, type is output.
C3 = LCELL( _EQ005 $ GND);
_EQ005 = FF8 & !LOA & LOB
# FF8 & LOA & !LOB;
-- Node name is 'C4'
-- Equation name is 'C4', location is LC013, type is output.
C4 = LCELL( _EQ006 $ GND);
_EQ006 = FF9 & !LOA & LOB
# FF9 & LOA & !LOB;
-- Node name is 'C5'
-- Equation name is 'C5', location is LC030, type is output.
C5 = LCELL( _EQ007 $ GND);
_EQ007 = FF10 & !LOB;
-- Node name is 'C6'
-- Equation name is 'C6', location is LC031, type is output.
C6 = LCELL( _EQ008 $ GND);
_EQ008 = FF11 & !LOB;
-- Node name is 'C7'
-- Equation name is 'C7', location is LC014, type is output.
C7 = LCELL( _EQ009 $ GND);
_EQ009 = FF12 & !LOB;
-- Node name is 'C8'
-- Equation name is 'C8', location is LC015, type is output.
C8 = LCELL( _EQ010 $ GND);
_EQ010 = FF13 & !LOB;
-- Node name is 'C9'
-- Equation name is 'C9', location is LC007, type is output.
C9 = LCELL( _EQ011 $ GND);
_EQ011 = FF14 & !LOB;
-- Node name is 'FF0' from file "shuru.tdf" line 7, column 3
-- Equation name is 'FF0', location is LC020, type is buried.
FF0 = LCELL( _EQ012 $ GND);
_EQ012 = A0 & !LOA & LOB
# FF0 & LOA
# FF0 & !LOB
# A0 & FF0 & LOB
# A0 & FF0 & !LOA;
-- Node name is 'FF1' from file "shuru.tdf" line 7, column 3
-- Equation name is 'FF1', location is LC019, type is buried.
FF1 = LCELL( _EQ013 $ GND);
_EQ013 = A1 & !LOA & LOB
# FF1 & LOA
# FF1 & !LOB
# A1 & FF1 & LOB
# A1 & FF1 & !LOA;
-- Node name is 'FF2' from file "shuru.tdf" line 7, column 3
-- Equation name is 'FF2', location is LC001, type is buried.
FF2 = LCELL( _EQ014 $ GND);
_EQ014 = A2 & !LOA & LOB
# FF2 & LOA
# FF2 & !LOB
# A2 & FF2 & LOB
# A2 & FF2 & !LOA;
-- Node name is 'FF3' from file "shuru.tdf" line 7, column 3
-- Equation name is 'FF3', location is LC004, type is buried.
FF3 = LCELL( _EQ015 $ GND);
_EQ015 = A3 & !LOA & LOB
# FF3 & LOA
# FF3 & !LOB
# A3 & FF3 & LOB
# A3 & FF3 & !LOA;
-- Node name is 'FF4' from file "shuru.tdf" line 7, column 3
-- Equation name is 'FF4', location is LC005, type is buried.
FF4 = LCELL( _EQ016 $ GND);
_EQ016 = A4 & !LOA & LOB
# FF4 & LOA
# FF4 & !LOB
# A4 & FF4 & LOB
# A4 & FF4 & !LOA;
-- Node name is 'FF5~1' from file "shuru.tdf" line 7, column 3
-- Equation name is 'FF5~1', location is LC017, type is buried.
-- synthesized logic cell
_LC017 = LCELL( _EQ017 $ GND);
_EQ017 = FF0 & FF5 & LOA
# FF0 & FF5 & LOB
# FF0 & FF5 & !LOB
# FF0 & FF5 & !LOA;
-- Node name is 'FF5' from file "shuru.tdf" line 7, column 3
-- Equation name is 'FF5', location is LC021, type is buried.
FF5 = LCELL( _EQ018 $ GND);
_EQ018 = FF5 & LOA & LOB
# FF0 & LOA & !LOB
# FF0 & !LOA & LOB
# FF5 & !LOA & !LOB
# _LC017;
-- Node name is 'FF6~1' from file "shuru.tdf" line 7, column 3
-- Equation name is 'FF6~1', location is LC022, type is buried.
-- synthesized logic cell
_LC022 = LCELL( _EQ019 $ GND);
_EQ019 = FF1 & FF6 & LOA
# FF1 & FF6 & LOB
# FF1 & FF6 & !LOB
# FF1 & FF6 & !LOA;
-- Node name is 'FF6' from file "shuru.tdf" line 7, column 3
-- Equation name is 'FF6', location is LC023, type is buried.
FF6 = LCELL( _EQ020 $ GND);
_EQ020 = FF6 & LOA & LOB
# FF1 & LOA & !LOB
# FF1 & !LOA & LOB
# FF6 & !LOA & !LOB
# _LC022;
-- Node name is 'FF7~1' from file "shuru.tdf" line 7, column 3
-- Equation name is 'FF7~1', location is LC024, type is buried.
-- synthesized logic cell
_LC024 = LCELL( _EQ021 $ GND);
_EQ021 = FF2 & FF7 & LOA
# FF2 & FF7 & LOB
# FF2 & FF7 & !LOB
# FF2 & FF7 & !LOA;
-- Node name is 'FF7' from file "shuru.tdf" line 7, column 3
-- Equation name is 'FF7', location is LC025, type is buried.
FF7 = LCELL( _EQ022 $ GND);
_EQ022 = FF7 & LOA & LOB
# FF2 & LOA & !LOB
# FF2 & !LOA & LOB
# FF7 & !LOA & !LOB
# _LC024;
-- Node name is 'FF8~1' from file "shuru.tdf" line 7, column 3
-- Equation name is 'FF8~1', location is LC008, type is buried.
-- synthesized logic cell
_LC008 = LCELL( _EQ023 $ GND);
_EQ023 = FF3 & FF8 & LOA
# FF3 & FF8 & LOB
# FF3 & FF8 & !LOB
# FF3 & FF8 & !LOA;
-- Node name is 'FF8' from file "shuru.tdf" line 7, column 3
-- Equation name is 'FF8', location is LC011, type is buried.
FF8 = LCELL( _EQ024 $ GND);
_EQ024 = FF8 & LOA & LOB
# FF3 & LOA & !LOB
# FF3 & !LOA & LOB
# FF8 & !LOA & !LOB
# _LC008;
-- Node name is 'FF9~1' from file "shuru.tdf" line 7, column 3
-- Equation name is 'FF9~1', location is LC012, type is buried.
-- synthesized logic cell
_LC012 = LCELL( _EQ025 $ GND);
_EQ025 = FF4 & FF9 & LOA
# FF4 & FF9 & LOB
# FF4 & FF9 & !LOB
# FF4 & FF9 & !LOA;
-- Node name is 'FF9' from file "shuru.tdf" line 7, column 3
-- Equation name is 'FF9', location is LC016, type is buried.
FF9 = LCELL( _EQ026 $ GND);
_EQ026 = FF9 & LOA & LOB
# FF4 & LOA & !LOB
# FF4 & !LOA & LOB
# FF9 & !LOA & !LOB
# _LC012;
-- Node name is 'FF10' from file "shuru.tdf" line 7, column 3
-- Equation name is 'FF10', location is LC029, type is buried.
FF10 = LCELL( _EQ027 $ GND);
_EQ027 = FF10 & LOB
# A0 & !LOB
# A0 & FF10;
-- Node name is 'FF11' from file "shuru.tdf" line 7, column 3
-- Equation name is 'FF11', location is LC018, type is buried.
FF11 = LCELL( _EQ028 $ GND);
_EQ028 = FF11 & LOB
# A1 & !LOB
# A1 & FF11;
-- Node name is 'FF12' from file "shuru.tdf" line 7, column 3
-- Equation name is 'FF12', location is LC002, type is buried.
FF12 = LCELL( _EQ029 $ GND);
_EQ029 = FF12 & LOB
# A2 & !LOB
# A2 & FF12;
-- Node name is 'FF13' from file "shuru.tdf" line 7, column 3
-- Equation name is 'FF13', location is LC003, type is buried.
FF13 = LCELL( _EQ030 $ GND);
_EQ030 = FF13 & LOB
# A3 & !LOB
# A3 & FF13;
-- Node name is 'FF14' from file "shuru.tdf" line 7, column 3
-- Equation name is 'FF14', location is LC006, type is buried.
FF14 = LCELL( _EQ031 $ GND);
_EQ031 = FF14 & LOB
# A4 & !LOB
# A4 & FF14;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information c:\baowenlei\shuru.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 3,873K
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