📄 shuru.rpt
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Project Information c:\baowenlei\shuru.rpt
MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 04/10/2009 15:36:15
Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
Untitled
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
shuru EPM7032SLC44-5 7 11 0 31 0 96 %
User Pins: 7 11 0
Device-Specific Information: c:\baowenlei\shuru.rpt
shuru
***** Logic for device 'shuru' compiled without errors.
Device: EPM7032SLC44-5
Device Options:
Turbo Bit = ON
Security Bit = OFF
Enable JTAG Support = ON
User Code = ffff
Device-Specific Information: c:\baowenlei\shuru.rpt
shuru
** ERROR SUMMARY **
Info: Chip 'shuru' in device 'EPM7032SLC44-5' has less than 10% of logic cells available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
R R
E E
S S
E E
R R
L L V G G G G G V V
A O O C N N N N N E E
4 B A C D D D D D D D
-----------------------------------_
/ 6 5 4 3 2 1 44 43 42 41 40 |
#TDI | 7 39 | RESERVED
A3 | 8 38 | #TDO
A2 | 9 37 | RESERVED
GND | 10 36 | RESERVED
C9 | 11 35 | VCC
A0 | 12 EPM7032SLC44-5 34 | RESERVED
#TMS | 13 33 | RESERVED
C3 | 14 32 | #TCK
VCC | 15 31 | C0
A1 | 16 30 | GND
RESERVED | 17 29 | C1
|_ 18 19 20 21 22 23 24 25 26 27 28 _|
------------------------------------
C C C R G V A C C R C
4 7 8 E N C B 6 5 E 2
S D C L S
E E E
R R
V V
E E
D D
N.C. = No Connect. This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: c:\baowenlei\shuru.rpt
shuru
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 15/16( 93%) 14/16( 87%) 5/16( 31%) 15/36( 41%)
B: LC17 - LC32 16/16(100%) 8/16( 50%) 5/16( 31%) 15/36( 41%)
Total dedicated input pins used: 0/4 ( 0%)
Total I/O pins used: 22/32 ( 68%)
Total logic cells used: 31/32 ( 96%)
Total shareable expanders used: 0/32 ( 0%)
Total Turbo logic cells used: 31/32 ( 96%)
Total shareable expanders not available (n/a): 10/32 ( 31%)
Average fan-in: 3.45
Total fan-in: 107
Total input pins required: 7
Total fast input logic cells required: 0
Total output pins required: 11
Total bidirectional pins required: 0
Total reserved pins required 4
Total logic cells required: 31
Total flipflops required: 0
Total product terms required: 101
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 0
Synthesized logic cells: 5/ 32 ( 15%)
Device-Specific Information: c:\baowenlei\shuru.rpt
shuru
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
12 (8) (A) INPUT 0 0 0 0 0 0 2 A0
16 (11) (A) INPUT 0 0 0 0 0 0 2 A1
9 (6) (A) INPUT 0 0 0 0 0 0 2 A2
8 (5) (A) INPUT 0 0 0 0 0 0 2 A3
6 (3) (A) INPUT 0 0 0 0 0 0 2 A4
4 (1) (A) INPUT 0 0 0 0 0 6 15 LOA
5 (2) (A) INPUT 0 0 0 0 0 11 20 LOB
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: c:\baowenlei\shuru.rpt
shuru
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
24 32 B OUTPUT t 0 0 0 2 0 0 0 ABLE
31 26 B OUTPUT t 0 0 0 2 1 0 0 C0
29 27 B OUTPUT t 0 0 0 2 1 0 0 C1
28 28 B OUTPUT t 0 0 0 2 1 0 0 C2
14 10 A OUTPUT t 0 0 0 2 1 0 0 C3
18 13 A OUTPUT t 0 0 0 2 1 0 0 C4
26 30 B OUTPUT t 0 0 0 1 1 0 0 C5
25 31 B OUTPUT t 0 0 0 1 1 0 0 C6
19 14 A OUTPUT t 0 0 0 1 1 0 0 C7
20 15 A OUTPUT t 0 0 0 1 1 0 0 C8
11 7 A OUTPUT t 0 0 0 1 1 0 0 C9
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: c:\baowenlei\shuru.rpt
shuru
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(38) 20 B LCELL t 1 0 1 3 1 0 3 FF0
(39) 19 B LCELL t 1 0 1 3 1 0 3 FF1
(4) 1 A LCELL t 1 0 1 3 1 0 3 FF2
(7) 4 A LCELL t 1 0 1 3 1 0 3 FF3
(8) 5 A LCELL t 1 0 1 3 1 0 3 FF4
(41) 17 B LCELL s t 0 0 0 2 2 0 1 FF5~1
(37) 21 B LCELL t 1 0 1 2 3 1 2 FF5
(36) 22 B LCELL s t 0 0 0 2 2 0 1 FF6~1
(34) 23 B LCELL t 1 0 1 2 3 1 2 FF6
(33) 24 B LCELL s t 0 0 0 2 2 0 1 FF7~1
(32) 25 B LCELL t 1 0 1 2 3 1 2 FF7
(12) 8 A LCELL s t 0 0 0 2 2 0 1 FF8~1
(16) 11 A LCELL t 1 0 1 2 3 1 2 FF8
(17) 12 A LCELL s t 0 0 0 2 2 0 1 FF9~1
(21) 16 A LCELL t 1 0 1 2 3 1 2 FF9
(27) 29 B LCELL t 0 0 0 2 1 1 1 FF10
(40) 18 B LCELL t 0 0 0 2 1 1 1 FF11
(5) 2 A LCELL t 0 0 0 2 1 1 1 FF12
(6) 3 A LCELL t 0 0 0 2 1 1 1 FF13
(9) 6 A LCELL t 0 0 0 2 1 1 1 FF14
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: c:\baowenlei\shuru.rpt
shuru
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+----------------------------- LC10 C3
| +--------------------------- LC13 C4
| | +------------------------- LC14 C7
| | | +----------------------- LC15 C8
| | | | +--------------------- LC7 C9
| | | | | +------------------- LC1 FF2
| | | | | | +----------------- LC4 FF3
| | | | | | | +--------------- LC5 FF4
| | | | | | | | +------------- LC8 FF8~1
| | | | | | | | | +----------- LC11 FF8
| | | | | | | | | | +--------- LC12 FF9~1
| | | | | | | | | | | +------- LC16 FF9
| | | | | | | | | | | | +----- LC2 FF12
| | | | | | | | | | | | | +--- LC3 FF13
| | | | | | | | | | | | | | +- LC6 FF14
| | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | that feed LAB 'A'
LC | | | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'A':
LC1 -> - - - - - * - - - - - - - - - | * * | <-- FF2
LC4 -> - - - - - - * - * * - - - - - | * - | <-- FF3
LC5 -> - - - - - - - * - - * * - - - | * - | <-- FF4
LC8 -> - - - - - - - - - * - - - - - | * - | <-- FF8~1
LC11 -> * - - - - - - - * * - - - - - | * - | <-- FF8
LC12 -> - - - - - - - - - - - * - - - | * - | <-- FF9~1
LC16 -> - * - - - - - - - - * * - - - | * - | <-- FF9
LC2 -> - - * - - - - - - - - - * - - | * - | <-- FF12
LC3 -> - - - * - - - - - - - - - * - | * - | <-- FF13
LC6 -> - - - - * - - - - - - - - - * | * - | <-- FF14
Pin
9 -> - - - - - * - - - - - - * - - | * - | <-- A2
8 -> - - - - - - * - - - - - - * - | * - | <-- A3
6 -> - - - - - - - * - - - - - - * | * - | <-- A4
4 -> * * - - - * * * * * * * - - - | * * | <-- LOA
5 -> * * * * * * * * * * * * * * * | * * | <-- LOB
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: c:\baowenlei\shuru.rpt
shuru
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------------------- LC32 ABLE
| +----------------------------- LC26 C0
| | +--------------------------- LC27 C1
| | | +------------------------- LC28 C2
| | | | +----------------------- LC30 C5
| | | | | +--------------------- LC31 C6
| | | | | | +------------------- LC20 FF0
| | | | | | | +----------------- LC19 FF1
| | | | | | | | +--------------- LC17 FF5~1
| | | | | | | | | +------------- LC21 FF5
| | | | | | | | | | +----------- LC22 FF6~1
| | | | | | | | | | | +--------- LC23 FF6
| | | | | | | | | | | | +------- LC24 FF7~1
| | | | | | | | | | | | | +----- LC25 FF7
| | | | | | | | | | | | | | +--- LC29 FF10
| | | | | | | | | | | | | | | +- LC18 FF11
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC20 -> - - - - - - * - * * - - - - - - | - * | <-- FF0
LC19 -> - - - - - - - * - - * * - - - - | - * | <-- FF1
LC17 -> - - - - - - - - - * - - - - - - | - * | <-- FF5~1
LC21 -> - * - - - - - - * * - - - - - - | - * | <-- FF5
LC22 -> - - - - - - - - - - - * - - - - | - * | <-- FF6~1
LC23 -> - - * - - - - - - - * * - - - - | - * | <-- FF6
LC24 -> - - - - - - - - - - - - - * - - | - * | <-- FF7~1
LC25 -> - - - * - - - - - - - - * * - - | - * | <-- FF7
LC29 -> - - - - * - - - - - - - - - * - | - * | <-- FF10
LC18 -> - - - - - * - - - - - - - - - * | - * | <-- FF11
Pin
12 -> - - - - - - * - - - - - - - * - | - * | <-- A0
16 -> - - - - - - - * - - - - - - - * | - * | <-- A1
4 -> * * * * - - * * * * * * * * - - | * * | <-- LOA
5 -> * * * * * * * * * * * * * * * * | * * | <-- LOB
LC1 -> - - - - - - - - - - - - * * - - | * * | <-- FF2
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