📄 final.rpt
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Project Information f:\baowenlei\final.rpt
MAX+plus II Compiler Report File
Version 9.3 7/23/1999
Compiled: 04/19/2009 13:03:17
Copyright (C) 1988-1999 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
final EPM7128SLC84-15 7 31 0 109 66 85 %
User Pins: 7 31 0
Project Information f:\baowenlei\final.rpt
** PROJECT COMPILATION MESSAGES **
Warning: Primitive 'LEDC6' is stuck at VCC
Warning: Primitive 'LEDC5' is stuck at VCC
Warning: Primitive 'LEDC4' is stuck at VCC
Warning: Primitive 'LEDC3' is stuck at VCC
Warning: Primitive 'LEDC2' is stuck at VCC
Warning: Primitive 'LEDC1' is stuck at VCC
Project Information f:\baowenlei\final.rpt
** PIN/LOCATION/CHIP ASSIGNMENTS **
Actual
User Assignments
Assignments (if different) Node Name
final@33 BAO0
final@34 BAO1
final@35 BAO2
final@36 BAO3
final@37 BAO4
final@4 C0
final@20 C1
final@22 C2
final@21 C3
final@12 C4
final@5 C5
final@18 C6
final@15 C7
final@16 C8
final@17 C9
final@41 LEDA1
final@40 LEDA2
final@44 LEDA3
final@45 LEDA4
final@48 LEDA5
final@46 LEDA6
final@49 LEDA7
final@52 LEDB1
final@50 LEDB2
final@54 LEDB3
final@55 LEDB4
final@57 LEDB5
final@56 LEDB6
final@58 LEDB7
final@73 LEDC1
final@70 LEDC2
final@75 LEDC3
final@76 LEDC4
final@80 LEDC5
final@77 LEDC6
final@79 LEDC7
final@84 LOCK1
final@83 LOCK2
Project Information f:\baowenlei\final.rpt
** FILE HIERARCHY **
|chengfa:1|
|shuru:2|
|fuhao:7|
|xianshi:8|
Device-Specific Information: f:\baowenlei\final.rpt
final
***** Logic for device 'final' compiled without errors.
Device: EPM7128SLC84-15
Device Options:
Turbo Bit = ON
Security Bit = OFF
Enable JTAG Support = ON
User Code = ffff
MultiVolt I/O = OFF
R R R R R R
E E E E E E
S S S S S V S
E E E E E C L L E L L V L L L
R R R R R C O O R E E C E E E
V V V V G V I G G C C G V D D C D D D
E E E E N E C C N N N K K N E C C I C C C
D D D D D D 5 0 T D D 1 2 D D 5 7 O 6 4 3
-----------------------------------------------------------------_
/ 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |
C4 | 12 74 | RESERVED
VCCIO | 13 73 | LEDC1
#TDI | 14 72 | GND
C7 | 15 71 | #TDO
C8 | 16 70 | LEDC2
C9 | 17 69 | RESERVED
C6 | 18 68 | RESERVED
GND | 19 67 | RESERVED
C1 | 20 66 | VCCIO
C3 | 21 65 | RESERVED
C2 | 22 EPM7128SLC84-15 64 | RESERVED
#TMS | 23 63 | RESERVED
RESERVED | 24 62 | #TCK
RESERVED | 25 61 | RESERVED
VCCIO | 26 60 | RESERVED
RESERVED | 27 59 | GND
RESERVED | 28 58 | LEDB7
RESERVED | 29 57 | LEDB5
RESERVED | 30 56 | LEDB6
RESERVED | 31 55 | LEDB4
GND | 32 54 | LEDB3
|_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|
------------------------------------------------------------------
B B B B B V R L L G V L L L G L L L R L V
A A A A A C E E E N C E E E N E E E E E C
O O O O O C S D D D C D D D D D D D S D C
0 1 2 3 4 I E A A I A A A A A B E B I
O R 2 1 N 3 4 6 5 7 2 R 1 O
V T V
E E
D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: f:\baowenlei\final.rpt
final
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 15/16( 93%) 3/ 8( 37%) 16/16(100%) 17/36( 47%)
B: LC17 - LC32 16/16(100%) 8/ 8(100%) 11/16( 68%) 22/36( 61%)
C: LC33 - LC48 7/16( 43%) 1/ 8( 12%) 16/16(100%) 15/36( 41%)
D: LC49 - LC64 16/16(100%) 7/ 8( 87%) 16/16(100%) 31/36( 86%)
E: LC65 - LC80 11/16( 68%) 7/ 8( 87%) 16/16(100%) 25/36( 69%)
F: LC81 - LC96 15/16( 93%) 6/ 8( 75%) 16/16(100%) 18/36( 50%)
G: LC97 - LC112 13/16( 81%) 2/ 8( 25%) 16/16(100%) 17/36( 47%)
H: LC113 - LC128 16/16(100%) 6/ 8( 75%) 16/16(100%) 24/36( 66%)
Total dedicated input pins used: 2/4 ( 50%)
Total I/O pins used: 40/64 ( 62%)
Total logic cells used: 109/128 ( 85%)
Total shareable expanders used: 66/128 ( 51%)
Total Turbo logic cells used: 109/128 ( 85%)
Total shareable expanders not available (n/a): 57/128 ( 44%)
Average fan-in: 6.65
Total fan-in: 725
Total input pins required: 7
Total fast input logic cells required: 0
Total output pins required: 31
Total bidirectional pins required: 0
Total reserved pins required 4
Total logic cells required: 109
Total flipflops required: 0
Total product terms required: 473
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 50
Synthesized logic cells: 63/ 128 ( 49%)
Device-Specific Information: f:\baowenlei\final.rpt
final
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
33 (64) (D) INPUT 0 0 0 0 0 0 2 BAO0
34 (61) (D) INPUT 0 0 0 0 0 0 2 BAO1
35 (59) (D) INPUT 0 0 0 0 0 0 2 BAO2
36 (57) (D) INPUT 0 0 0 0 0 0 2 BAO3
37 (56) (D) INPUT 0 0 0 0 0 0 2 BAO4
84 - - INPUT 0 0 0 0 0 21 56 LOCK1
83 - - INPUT 0 0 0 0 0 25 61 LOCK2
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
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