📄 jieguo.rpt
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Project Information d:\baowenlei\jieguo.rpt
MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 04/10/2009 15:26:22
Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was unsuccessful
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
jieguo EPM7128SLC84-15 7 31 0 139 59 No Fit
User Pins: 7 31 0
Project Information d:\baowenlei\jieguo.rpt
** PROJECT COMPILATION MESSAGES **
Warning: Primitive 'LEDC6' is stuck at VCC
Warning: Primitive 'LEDC5' is stuck at VCC
Warning: Primitive 'LEDC4' is stuck at VCC
Warning: Primitive 'LEDC3' is stuck at VCC
Warning: Primitive 'LEDC2' is stuck at VCC
Warning: Primitive 'LEDC1' is stuck at VCC
Error: Project does not fit in specified device(s)
Error: No fit found, generating Report File
(See individual chip error summaries for additional information)
Project Information d:\baowenlei\jieguo.rpt
** PIN/LOCATION/CHIP ASSIGNMENTS **
Actual
User Assignments
Assignments (if different) Node Name
jieguo@33 --------- BAO0
jieguo@34 --------- BAO1
jieguo@35 --------- BAO2
jieguo@36 --------- BAO3
jieguo@37 --------- BAO4
jieguo@4 --------- C0
jieguo@20 --------- C1
jieguo@22 --------- C2
jieguo@21 --------- C3
jieguo@12 --------- C4
jieguo@5 --------- C5
jieguo@18 --------- C6
jieguo@15 --------- C7
jieguo@16 --------- C8
jieguo@17 --------- C9
jieguo@41 --------- LEDA1
jieguo@40 --------- LEDA2
jieguo@44 --------- LEDA3
jieguo@45 --------- LEDA4
jieguo@48 --------- LEDA5
jieguo@46 --------- LEDA6
jieguo@49 --------- LEDA7
jieguo@52 --------- LEDB1
jieguo@50 --------- LEDB2
jieguo@54 --------- LEDB3
jieguo@55 --------- LEDB4
jieguo@57 --------- LEDB5
jieguo@56 --------- LEDB6
jieguo@58 --------- LEDB7
jieguo@73 --------- LEDC1
jieguo@70 --------- LEDC2
jieguo@75 --------- LEDC3
jieguo@76 --------- LEDC4
jieguo@80 --------- LEDC5
jieguo@77 --------- LEDC6
jieguo@79 --------- LEDC7
jieguo@84 --------- LOCK1
jieguo@83 --------- LOCK2
Project Information d:\baowenlei\jieguo.rpt
** FILE HIERARCHY **
|chengfa:19|
|fuhao:20|
|xianshi:21|
|shuru:22|
Device-Specific Information: d:\baowenlei\jieguo.rpt
jieguo
***** Logic for device 'jieguo' contains errors -- see ERROR SUMMARY.
Device: EPM7128SLC84-15
Device Options:
Turbo Bit = ON
Security Bit = OFF
Enable JTAG Support = ON
User Code = ffff
MultiVolt I/O = OFF
Device-Specific Information: d:\baowenlei\jieguo.rpt
jieguo
** ERROR SUMMARY **
Error: Project requires too many (139/128) logic cells
Error: Project requires too many (136/128) shareable expanders
Device-Specific Information: d:\baowenlei\jieguo.rpt
jieguo
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 3/16( 18%) 3/ 8( 37%) 4/16( 25%) 5/36( 13%)
B: LC17 - LC32 7/16( 43%) 8/ 8(100%) 0/16( 0%) 9/36( 25%)
C: LC33 - LC48 0/16( 0%) 1/ 8( 12%) 0/16( 0%) 0/36( 0%)
D: LC49 - LC64 2/16( 12%) 7/ 8( 87%) 3/16( 18%) 9/36( 25%)
E: LC65 - LC80 7/16( 43%) 7/ 8( 87%) 20/16(125%) 32/36( 88%)
F: LC81 - LC96 5/16( 31%) 6/ 8( 75%) 16/16(100%) 36/36(100%)
G: LC97 - LC112 1/16( 6%) 2/ 8( 25%) 0/16( 0%) 0/36( 0%)
H: LC113 - LC128 6/16( 37%) 6/ 8( 75%) 2/16( 12%) 6/36( 16%)
Total dedicated input pins used: 0/4 ( 0%)
Total I/O pins used: 0/64 ( 0%)
Total logic cells used: 0/128 ( 0%)
Total shareable expanders used: 0/128 ( 0%)
Total Turbo logic cells used: 139/128 (108%)
Total shareable expanders not available (n/a): 77/128 ( 60%)
Average fan-in: 8.62
Total fan-in: 1199
Total input pins required: 7
Total fast input logic cells required: 0
Total output pins required: 31
Total bidirectional pins required: 0
Total reserved pins required 4
Total logic cells required: 139
Total flipflops required: 0
Total product terms required: 539
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 59
Synthesized logic cells: 93/ 128 ( 72%)
Device-Specific Information: d:\baowenlei\jieguo.rpt
jieguo
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
33 (64) (D) INPUT 0 0 0 0 0 0 4 BAO0
34 (61) (D) INPUT 0 0 0 0 0 0 4 BAO1
35 (59) (D) INPUT 0 0 0 0 0 0 4 BAO2
36 (57) (D) INPUT 0 0 0 0 0 0 4 BAO3
37 (56) (D) INPUT 0 0 0 0 0 0 4 BAO4
84 - - INPUT 0 0 0 0 0 21 70 LOCK1
83 - - INPUT 0 0 0 0 0 25 70 LOCK2
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\baowenlei\jieguo.rpt
jieguo
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
4 16 A OUTPUT t 2 1 0 2 1 0 0 C0
20 21 B OUTPUT t 0 0 0 2 1 0 0 C1
22 17 B OUTPUT t 0 0 0 2 1 0 0 C2
21 19 B OUTPUT t 0 0 0 2 1 0 0 C3
12 3 A OUTPUT t 0 0 0 2 1 0 0 C4
5 14 A OUTPUT t 2 2 0 2 1 0 0 C5
18 24 B OUTPUT t 0 0 0 1 1 0 0 C6
15 29 B OUTPUT t 0 0 0 1 1 0 0 C7
16 27 B OUTPUT t 0 0 0 1 1 0 0 C8
17 25 B OUTPUT t 0 0 0 1 1 0 0 C9
41 49 D OUTPUT t 3 2 1 2 6 0 0 LEDA1
40 51 D OUTPUT t 1 1 0 2 6 0 0 LEDA2
44 65 E OUTPUT t 2 2 0 2 6 0 0 LEDA3
45 67 E OUTPUT t 3 1 0 2 8 0 0 LEDA4
48 72 E OUTPUT t 6 1 1 2 7 0 0 LEDA5
46 69 E OUTPUT t 2 1 1 2 7 0 0 LEDA6
49 73 E OUTPUT t 0 0 0 2 8 0 0 LEDA7
52 80 E OUTPUT t 5 4 1 2 17 0 0 LEDB1
50 75 E OUTPUT t 9 5 1 2 17 0 0 LEDB2
54 83 F OUTPUT t 9 5 1 2 14 0 0 LEDB3
55 85 F OUTPUT t 4 1 0 2 16 0 0 LEDB4
57 88 F OUTPUT t 3 1 0 2 12 0 0 LEDB5
56 86 F OUTPUT t 5 4 1 2 15 0 0 LEDB6
58 91 F OUTPUT t 0 0 0 2 8 0 0 LEDB7
73 115 H OUTPUT t 0 0 0 0 0 0 0 LEDC1
70 109 G OUTPUT t 0 0 0 0 0 0 0 LEDC2
75 118 H OUTPUT t 0 0 0 0 0 0 0 LEDC3
76 120 H OUTPUT t 0 0 0 0 0 0 0 LEDC4
80 126 H OUTPUT t 0 0 0 0 0 0 0 LEDC5
77 123 H OUTPUT t 0 0 0 0 0 0 0 LEDC6
79 125 H OUTPUT t 2 2 0 2 4 0 0 LEDC7
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\baowenlei\jieguo.rpt
jieguo
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
- ?? ?? SOFT s t 0 0 0 2 6 0 2 |chengfa:19|JWC3~1
- ?? ?? SOFT s t 2 0 1 2 7 7 4 |chengfa:19|~453~1
- ?? ?? SOFT s t 1 0 1 0 6 0 1 |chengfa:19|~453~2
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