📄 chengfa.rpt
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# !A1 & !A2 & A3 & A4 & Z1 & Z2
# A1 & A3 & !Z1 & Z2 & Z4;
-- Node name is '~850~4' from file "chengfa.tdf" line 44, column 9
-- Equation name is '~850~4', location is LC042, type is buried.
-- synthesized logic cell
_LC042 = LCELL( _EQ021 $ GND);
_EQ021 = !A1 & A2 & A4 & Z1 & Z3
# A1 & !A3 & !Z1 & Z2 & !Z4
# !A1 & A2 & !A4 & Z1 & !Z3
# !Z1 & !Z2 & !Z3 & !Z4
# !A4 & !Z2 & !Z3 & !Z4;
-- Node name is '~850~5' from file "chengfa.tdf" line 44, column 9
-- Equation name is '~850~5', location is LC045, type is buried.
-- synthesized logic cell
_LC045 = LCELL( _EQ022 $ GND);
_EQ022 = !A2 & !A3 & !A4 & !Z4
# !A2 & !Z1 & !Z2 & !Z4
# !A1 & !Z1 & !Z2 & !Z3
# !A1 & !A3 & !Z1 & !Z3
# !A1 & !A2 & !A3 & !A4;
-- Node name is '~850~6' from file "chengfa.tdf" line 44, column 9
-- Equation name is '~850~6', location is LC054, type is buried.
-- synthesized logic cell
_LC054 = LCELL( _EQ023 $ GND);
_EQ023 = !A1 & !A2 & !Z1 & !Z2
# !A1 & !A2 & !A4 & !Z2
# !A1 & !A2 & !A3 & !Z1;
-- Node name is '~851~1' from file "chengfa.tdf" line 44, column 9
-- Equation name is '~851~1', location is LC056, type is buried.
-- synthesized logic cell
_LC056 = LCELL( _EQ024 $ GND);
_EQ024 = ABLE & A1 & A2 & !A3 & A4 & Z1 & Z2 & !Z3 & Z4
# ABLE & A1 & A2 & A3 & !A4 & Z1 & Z2 & !Z4
# ABLE & A2 & !A3 & A4 & Z1 & !Z2 & Z3 & !Z4
# ABLE & A1 & !A2 & A4 & Z1 & !Z2 & !Z3 & Z4
# ABLE & A1 & !A2 & !A3 & A4 & Z1 & !Z2 & Z4;
-- Node name is '~851~2' from file "chengfa.tdf" line 44, column 9
-- Equation name is '~851~2', location is LC055, type is buried.
-- synthesized logic cell
_LC055 = LCELL( _EQ025 $ GND);
_EQ025 = ABLE & A2 & A3 & !A4 & Z1 & Z2 & !Z3 & !Z4
# ABLE & A1 & !A2 & A3 & !A4 & Z2 & !Z3 & Z4
# ABLE & A1 & A2 & !A3 & !A4 & Z2 & Z3 & !Z4
# ABLE & A1 & A4 & !Z1 & Z2 & Z3 & Z4
# ABLE & A1 & A3 & A4 & !Z1 & Z3 & Z4;
-- Node name is '~851~3' from file "chengfa.tdf" line 44, column 9
-- Equation name is '~851~3', location is LC050, type is buried.
-- synthesized logic cell
_LC050 = LCELL( _EQ026 $ GND);
_EQ026 = ABLE & !A1 & A2 & A3 & A4 & Z1 & Z4
# ABLE & A1 & A2 & A3 & A4 & !Z1 & Z2
# ABLE & !A1 & A4 & Z1 & Z2 & Z3 & Z4
# ABLE & !A1 & A3 & Z1 & Z2 & Z3 & Z4
# ABLE & !A2 & A4 & Z1 & Z2 & Z3 & !Z4;
-- Node name is '~851~4' from file "chengfa.tdf" line 44, column 9
-- Equation name is '~851~4', location is LC057, type is buried.
-- synthesized logic cell
_LC057 = LCELL( _EQ027 $ GND);
_EQ027 = ABLE & A1 & A2 & A3 & !A4 & !Z2 & Z4
# ABLE & !A1 & A2 & A4 & !Z1 & Z2 & !Z4
# ABLE & !A1 & A2 & !A4 & !Z1 & Z2 & Z4
# ABLE & !A1 & !A2 & A4 & !Z1 & Z2 & !Z3
# ABLE & !A1 & !A3 & A4 & Z2 & !Z3 & !Z4;
-- Node name is '~851~5' from file "chengfa.tdf" line 44, column 9
-- Equation name is '~851~5', location is LC059, type is buried.
-- synthesized logic cell
_LC059 = LCELL( _EQ028 $ GND);
_EQ028 = ABLE & !A2 & A3 & !A4 & !Z2 & Z3 & !Z4
# ABLE & !A2 & A3 & !A4 & !Z1 & Z3 & !Z4
# ABLE & !A1 & A3 & !A4 & !Z2 & Z3 & !Z4
# ABLE & !A1 & A2 & !A3 & !Z1 & !Z2 & Z4
# ABLE & A2 & !A3 & !A4 & !Z1 & !Z3 & Z4;
-- Node name is '~851~6' from file "chengfa.tdf" line 44, column 9
-- Equation name is '~851~6', location is LC061, type is buried.
-- synthesized logic cell
_LC061 = LCELL( _EQ029 $ GND);
_EQ029 = ABLE & !A1 & !A2 & A3 & Z1 & Z3
# ABLE & !A2 & !A3 & A4 & !Z1 & Z2
# ABLE & !A2 & !A3 & A4 & Z2 & !Z4
# ABLE & !A1 & !A2 & !A3 & A4 & Z2
# ABLE & A4 & !Z1 & Z2 & !Z3 & !Z4;
-- Node name is '~851~7' from file "chengfa.tdf" line 44, column 9
-- Equation name is '~851~7', location is LC062, type is buried.
-- synthesized logic cell
_LC062 = LCELL( _EQ030 $ GND);
_EQ030 = ABLE & !A2 & A3 & !Z1 & !Z2 & Z3
# ABLE & A3 & !Z1 & !Z2 & Z3 & !Z4
# ABLE & !A1 & !A2 & A3 & !A4 & Z3
# ABLE & A2 & !A4 & !Z2 & !Z3 & Z4
# ABLE & !A1 & A2 & !Z2 & !Z3 & Z4;
-- Node name is '~852~1' from file "chengfa.tdf" line 44, column 9
-- Equation name is '~852~1', location is LC063, type is buried.
-- synthesized logic cell
_LC063 = LCELL( _EQ031 $ GND);
_EQ031 = ABLE & A1 & !A2 & A4 & Z1 & !Z2 & Z3 & Z4
# ABLE & A1 & A3 & !A4 & Z1 & Z2 & Z3 & !Z4
# ABLE & A1 & !A3 & A4 & Z1 & Z2 & !Z3 & Z4
# ABLE & A1 & A2 & A3 & !A4 & Z1 & Z3 & !Z4
# ABLE & A1 & A2 & !A3 & A4 & Z1 & !Z3 & Z4;
-- Node name is '~852~2' from file "chengfa.tdf" line 44, column 9
-- Equation name is '~852~2', location is LC064, type is buried.
-- synthesized logic cell
_LC064 = LCELL( _EQ032 $ GND);
_EQ032 = ABLE & A1 & A2 & Z1 & Z2 & Z3 & Z4
# ABLE & A1 & A2 & A4 & Z1 & Z2 & !Z3
# ABLE & A1 & A2 & !A4 & Z2 & Z3 & Z4
# ABLE & A1 & A2 & !A3 & Z1 & Z2 & Z4
# ABLE & A2 & A3 & A4 & Z1 & Z2 & !Z4;
-- Node name is '~852~3' from file "chengfa.tdf" line 44, column 9
-- Equation name is '~852~3', location is LC051, type is buried.
-- synthesized logic cell
_LC051 = LCELL( _EQ033 $ GND);
_EQ033 = ABLE & !A2 & A4 & !Z1 & Z2 & Z3 & Z4
# ABLE & !A1 & !A2 & A4 & Z2 & Z3 & Z4
# ABLE & !A1 & A2 & A3 & A4 & !Z2 & Z4
# ABLE & A2 & A3 & A4 & !Z1 & !Z2 & Z4
# ABLE & A2 & !A3 & A4 & Z2 & !Z3 & Z4;
-- Node name is '~852~4' from file "chengfa.tdf" line 44, column 9
-- Equation name is '~852~4', location is LC052, type is buried.
-- synthesized logic cell
_LC052 = LCELL( _EQ034 $ GND);
_EQ034 = ABLE & A2 & A3 & !A4 & Z2 & Z3 & !Z4
# ABLE & A3 & A4 & Z1 & Z2 & !Z3 & !Z4
# ABLE & A1 & A2 & !A3 & !A4 & Z3 & Z4
# ABLE & !A1 & A2 & A4 & !Z1 & !Z2 & Z3
# ABLE & !A1 & !A2 & A3 & !Z1 & Z2 & Z4;
-- Node name is '~852~5' from file "chengfa.tdf" line 44, column 9
-- Equation name is '~852~5', location is LC053, type is buried.
-- synthesized logic cell
_LC053 = LCELL( _EQ035 $ GND);
_EQ035 = ABLE & !A1 & !A3 & A4 & !Z1 & Z3 & !Z4
# ABLE & !A2 & A3 & !A4 & !Z1 & !Z2 & Z4
# ABLE & !A1 & !A2 & A4 & !Z2 & Z3 & !Z4
# ABLE & !A1 & A3 & !A4 & !Z1 & !Z3 & Z4
# ABLE & !A2 & !A3 & A4 & Z3 & !Z4;
-- Node name is '~852~6' from file "chengfa.tdf" line 44, column 9
-- Equation name is '~852~6', location is LC039, type is buried.
-- synthesized logic cell
_LC039 = LCELL( _EQ036 $ GND);
_EQ036 = ABLE & !A2 & !A3 & A4 & !Z2 & Z3
# ABLE & !A2 & A3 & !A4 & !Z3 & Z4
# ABLE & !A1 & !A2 & A3 & !A4 & Z4
# ABLE & !A3 & A4 & !Z2 & Z3 & !Z4
# ABLE & A4 & !Z1 & !Z2 & Z3 & !Z4;
-- Node name is '~853~1~2' from file "chengfa.tdf" line 44, column 9
-- Equation name is '~853~1~2', location is LC040, type is buried.
-- synthesized logic cell
_LC040 = LCELL( _EQ037 $ GND);
_EQ037 = ABLE & A1 & !A2 & A3 & !A4 & Z1 & Z3 & Z4
# ABLE & A1 & A2 & A3 & !A4 & Z2 & !Z3 & Z4
# ABLE & A1 & !A2 & A3 & !A4 & Z2 & Z3 & Z4
# ABLE & A2 & A3 & !A4 & Z1 & Z2 & !Z3 & Z4
# ABLE & A1 & A3 & A4 & Z1 & Z2 & Z3;
-- Node name is '~853~1~3' from file "chengfa.tdf" line 44, column 9
-- Equation name is '~853~1~3', location is LC041, type is buried.
-- synthesized logic cell
_LC041 = LCELL( _EQ038 $ GND);
_EQ038 = ABLE & A1 & A2 & A3 & A4 & Z1 & Z3
# ABLE & A1 & A3 & A4 & Z1 & Z3 & !Z4
# ABLE & A2 & A3 & A4 & Z1 & Z3 & !Z4
# ABLE & A1 & A2 & A4 & Z2 & Z3 & !Z4
# ABLE & A2 & A4 & Z1 & Z2 & Z3 & !Z4;
-- Shareable expanders that are duplicated in multiple LABs:
-- _X001 occurs in LABs C, D
Project Information c:\baowenlei\chengfa.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 4,034K
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