📄 chengfa.rpt
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LC52 -> * - - | - * - - | <-- ~852~4
LC53 -> * - - | - * - - | <-- ~852~5
LC39 -> * - - | - * - - | <-- ~852~6
LC40 -> - * - | - * - - | <-- ~853~1~2
LC41 -> - * - | - * - - | <-- ~853~1~3
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: c:\baowenlei\chengfa.rpt
chengfa
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+------------------------------- LC36 ADDOUT1
| +----------------------------- LC46 ADDOUT2
| | +--------------------------- LC33 ADDOUT3
| | | +------------------------- LC35 ADDOUT4
| | | | +----------------------- LC37 ~753~1
| | | | | +--------------------- LC34 ~753~2
| | | | | | +------------------- LC38 ~753~3
| | | | | | | +----------------- LC43 ~849~1
| | | | | | | | +--------------- LC44 ~850~1
| | | | | | | | | +------------- LC47 ~850~2
| | | | | | | | | | +----------- LC48 ~850~3
| | | | | | | | | | | +--------- LC42 ~850~4
| | | | | | | | | | | | +------- LC45 ~850~5
| | | | | | | | | | | | | +----- LC39 ~852~6
| | | | | | | | | | | | | | +--- LC40 ~853~1~2
| | | | | | | | | | | | | | | +- LC41 ~853~1~3
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'C'
LC | | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'C':
LC34 -> - - - - * - - - - - - - - - - - | - - * - | <-- ~753~2
LC38 -> - - - - * - - - - - - - - - - - | - - * - | <-- ~753~3
LC43 -> - - * - - - - - - - - - - - - - | - - * - | <-- ~849~1
LC44 -> - - - * - - - - - - - - - - - - | - - * - | <-- ~850~1
LC47 -> - - - * - - - - - - - - - - - - | - - * - | <-- ~850~2
LC48 -> - - - * - - - - - - - - - - - - | - - * - | <-- ~850~3
LC42 -> - - - * - - - - - - - - - - - - | - - * - | <-- ~850~4
LC45 -> - - - * - - - - - - - - - - - - | - - * - | <-- ~850~5
Pin
4 -> * * * * * - - - - - - - - * * * | - * * * | <-- ABLE
21 -> * * * * * * - * * * * * * * * * | - - * * | <-- A1
11 -> - * * * * * * * * * * * * * * * | - * * * | <-- A2
12 -> - - * * * * * * * * * * * * * * | - * * * | <-- A3
5 -> - - - * - * * - * * * * * * * * | - * * * | <-- A4
20 -> * * * * * * - * * * * * * * * * | - - * * | <-- Z1
9 -> - * * * * * - * * * * * * * * * | - * * * | <-- Z2
8 -> - - * * * * * * * * * * * * * * | - * * * | <-- Z3
6 -> - - - * * - - - * * * * * * * * | - * * * | <-- Z4
LC54 -> - - - * - - - - - - - - - - - - | - - * - | <-- ~850~6
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: c:\baowenlei\chengfa.rpt
chengfa
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+------------------------------- LC49 ADDOUT5
| +----------------------------- LC58 ~828~1
| | +--------------------------- LC60 ~835~1
| | | +------------------------- LC54 ~850~6
| | | | +----------------------- LC56 ~851~1
| | | | | +--------------------- LC55 ~851~2
| | | | | | +------------------- LC50 ~851~3
| | | | | | | +----------------- LC57 ~851~4
| | | | | | | | +--------------- LC59 ~851~5
| | | | | | | | | +------------- LC61 ~851~6
| | | | | | | | | | +----------- LC62 ~851~7
| | | | | | | | | | | +--------- LC63 ~852~1
| | | | | | | | | | | | +------- LC64 ~852~2
| | | | | | | | | | | | | +----- LC51 ~852~3
| | | | | | | | | | | | | | +--- LC52 ~852~4
| | | | | | | | | | | | | | | +- LC53 ~852~5
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'D'
LC | | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'D':
LC56 -> * - - - - - - - - - - - - - - - | - - - * | <-- ~851~1
LC55 -> * - - - - - - - - - - - - - - - | - - - * | <-- ~851~2
LC50 -> * - - - - - - - - - - - - - - - | - - - * | <-- ~851~3
LC57 -> * - - - - - - - - - - - - - - - | - - - * | <-- ~851~4
LC59 -> * - - - - - - - - - - - - - - - | - - - * | <-- ~851~5
LC61 -> * - - - - - - - - - - - - - - - | - - - * | <-- ~851~6
LC62 -> * - - - - - - - - - - - - - - - | - - - * | <-- ~851~7
Pin
4 -> * * * - * * * * * * * * * * * * | - * * * | <-- ABLE
21 -> * * * * * * * * * * * * * * * * | - - * * | <-- A1
11 -> * * * * * * * * * * * * * * * * | - * * * | <-- A2
12 -> * * * * * * * * * * * * * * * * | - * * * | <-- A3
5 -> * * * * * * * * * * * * * * * * | - * * * | <-- A4
20 -> * - * * * * * * * * * * * * * * | - - * * | <-- Z1
9 -> * - * * * * * * * * * * * * * * | - * * * | <-- Z2
8 -> * * * - * * * * * * * * * * * * | - * * * | <-- Z3
6 -> * * * - * * * * * * * * * * * * | - * * * | <-- Z4
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: c:\baowenlei\chengfa.rpt
chengfa
** EQUATIONS **
ABLE : INPUT;
A1 : INPUT;
A2 : INPUT;
A3 : INPUT;
A4 : INPUT;
Z1 : INPUT;
Z2 : INPUT;
Z3 : INPUT;
Z4 : INPUT;
-- Node name is 'ADDOUT1'
-- Equation name is 'ADDOUT1', location is LC036, type is output.
ADDOUT1 = LCELL( _EQ001 $ GND);
_EQ001 = ABLE & A1 & Z1;
-- Node name is 'ADDOUT2'
-- Equation name is 'ADDOUT2', location is LC046, type is output.
ADDOUT2 = LCELL( _EQ002 $ GND);
_EQ002 = ABLE & !A1 & A2 & Z1
# ABLE & A2 & Z1 & !Z2
# ABLE & A1 & !A2 & Z2
# ABLE & A1 & !Z1 & Z2;
-- Node name is 'ADDOUT3'
-- Equation name is 'ADDOUT3', location is LC033, type is output.
ADDOUT3 = LCELL( _EQ003 $ _EQ004);
_EQ003 = ABLE & !A1 & A2 & A3 & !_LC043 & _X001 & Z1 & Z2
# ABLE & A1 & A2 & !_LC043 & _X001 & !Z1 & Z2 & Z3
# ABLE & A1 & A3 & !_LC043 & _X001 & Z1 & Z3
# ABLE & A1 & !A3 & !_LC043 & _X001 & Z1 & !Z3;
_X001 = EXP(!A1 & !A2 & !Z1);
_EQ004 = ABLE & !_LC043 & _X001;
_X001 = EXP(!A1 & !A2 & !Z1);
-- Node name is 'ADDOUT4'
-- Equation name is 'ADDOUT4', location is LC035, type is output.
ADDOUT4 = LCELL( _EQ005 $ _EQ006);
_EQ005 = ABLE & A1 & !A2 & A3 & A4 & !_LC042 & !_LC044 & !_LC045 &
!_LC047 & !_LC048 & !_LC054 & !Z2 & Z3 & !Z4
# ABLE & A1 & A2 & !A3 & A4 & !_LC042 & !_LC044 & !_LC045 &
!_LC047 & !_LC048 & !_LC054 & Z2 & !Z3 & !Z4
# ABLE & !A2 & A3 & !A4 & !_LC042 & !_LC044 & !_LC045 & !_LC047 &
!_LC048 & !_LC054 & Z1 & !Z2 & Z3 & Z4
# ABLE & A2 & !A3 & !A4 & !_LC042 & !_LC044 & !_LC045 & !_LC047 &
!_LC048 & !_LC054 & Z1 & Z2 & !Z3 & Z4;
_EQ006 = ABLE & !_LC042 & !_LC044 & !_LC045 & !_LC047 & !_LC048 & !_LC054;
-- Node name is 'ADDOUT5'
-- Equation name is 'ADDOUT5', location is LC049, type is output.
ADDOUT5 = LCELL( _EQ007 $ VCC);
_EQ007 = !_LC050 & !_LC055 & !_LC056 & !_LC057 & !_LC059 & !_LC061 &
!_LC062 & _X002 & _X003;
_X002 = EXP( ABLE & A2 & !Z1 & !Z2 & !Z3 & Z4);
_X003 = EXP( ABLE & !A1 & A2 & !A3 & !A4 & Z4);
-- Node name is 'ADDOUT6'
-- Equation name is 'ADDOUT6', location is LC024, type is output.
ADDOUT6 = LCELL( _EQ008 $ VCC);
_EQ008 = !_LC039 & !_LC051 & !_LC052 & !_LC053 & !_LC063 & !_LC064 & _X004 &
_X005;
_X004 = EXP( ABLE & !A2 & A3 & !Z2 & !Z3 & Z4);
_X005 = EXP( ABLE & A3 & !A4 & !Z2 & !Z3 & Z4);
-- Node name is 'ADDOUT7'
-- Equation name is 'ADDOUT7', location is LC021, type is output.
ADDOUT7 = LCELL( _EQ009 $ ABLE);
_EQ009 = ABLE & !_LC037 & !_LC040 & !_LC041 & _X006 & _X007;
_X006 = EXP( ABLE & A2 & A3 & A4 & Z2 & Z3);
_X007 = EXP( ABLE & A3 & A4 & Z2 & Z3 & !Z4);
-- Node name is 'ADDOUT8'
-- Equation name is 'ADDOUT8', location is LC020, type is output.
ADDOUT8 = LCELL( _EQ010 $ ABLE);
_EQ010 = ABLE & !_LC058 & !_LC060;
-- Node name is '~753~1' from file "chengfa.tdf" line 41, column 35
-- Equation name is '~753~1', location is LC037, type is buried.
-- synthesized logic cell
_LC037 = LCELL( _EQ011 $ _EQ012);
_EQ011 = ABLE & A1 & A2 & A3 & !_LC034 & !_LC038 & Z1 & !Z3 & Z4
# ABLE & A1 & !A2 & !_LC034 & !_LC038 & Z1 & Z2 & Z3 & Z4
# ABLE & A1 & A3 & !_LC034 & !_LC038 & Z2 & !Z3 & Z4
# ABLE & A3 & !_LC034 & !_LC038 & Z1 & Z2 & !Z3 & Z4;
_EQ012 = ABLE & !_LC034 & !_LC038 & Z4;
-- Node name is '~753~2' from file "chengfa.tdf" line 41, column 35
-- Equation name is '~753~2', location is LC034, type is buried.
-- synthesized logic cell
_LC034 = LCELL( _EQ013 $ GND);
_EQ013 = A2 & A3 & Z2 & !Z3
# A2 & !A3 & Z1 & Z3
# A1 & A2 & !A3 & Z3
# A2 & !A3 & Z2 & Z3
# A3 & A4 & Z3;
-- Node name is '~753~3' from file "chengfa.tdf" line 41, column 35
-- Equation name is '~753~3', location is LC038, type is buried.
-- synthesized logic cell
_LC038 = LCELL( _EQ014 $ GND);
_EQ014 = !A2 & A3 & Z3
# !A3 & !A4
# !A4 & !Z3;
-- Node name is '~828~1' from file "chengfa.tdf" line 41, column 35
-- Equation name is '~828~1', location is LC058, type is buried.
-- synthesized logic cell
_LC058 = LCELL( _EQ015 $ GND);
_EQ015 = ABLE & A1 & A2 & A4 & Z3 & Z4
# ABLE & A3 & A4 & Z3 & Z4;
-- Node name is '~835~1' from file "chengfa.tdf" line 41, column 75
-- Equation name is '~835~1', location is LC060, type is buried.
-- synthesized logic cell
_LC060 = LCELL( _EQ016 $ GND);
_EQ016 = ABLE & A1 & !A2 & !A3 & A4 & Z1 & Z2 & Z3 & Z4
# ABLE & A1 & A2 & A3 & A4 & Z1 & !Z3 & Z4
# ABLE & !A1 & A2 & !A3 & A4 & _X008 & Z3 & Z4
# ABLE & A3 & A4 & _X001 & Z2 & !Z3 & Z4;
_X008 = EXP(!Z1 & !Z2);
_X001 = EXP(!A1 & !A2 & !Z1);
-- Node name is '~849~1' from file "chengfa.tdf" line 44, column 9
-- Equation name is '~849~1', location is LC043, type is buried.
-- synthesized logic cell
_LC043 = LCELL( _EQ017 $ GND);
_EQ017 = !Z1 & !Z2 & !Z3
# !A2 & !Z1 & !Z3
# !A1 & !Z1 & !Z2
# !A1 & !A3 & !Z2
# !A1 & !A2 & !A3;
-- Node name is '~850~1' from file "chengfa.tdf" line 44, column 9
-- Equation name is '~850~1', location is LC044, type is buried.
-- synthesized logic cell
_LC044 = LCELL( _EQ018 $ GND);
_EQ018 = A1 & A2 & !A3 & !A4 & !Z2 & Z3 & Z4
# A1 & !A2 & A3 & !A4 & Z2 & !Z3 & Z4
# A2 & !A3 & A4 & Z1 & !Z2 & Z3 & !Z4
# !A2 & A3 & A4 & Z1 & Z2 & !Z3 & !Z4
# A1 & A2 & A3 & A4 & Z3 & Z4;
-- Node name is '~850~2' from file "chengfa.tdf" line 44, column 9
-- Equation name is '~850~2', location is LC047, type is buried.
-- synthesized logic cell
_LC047 = LCELL( _EQ019 $ GND);
_EQ019 = A1 & A2 & A3 & A4 & Z2 & Z4
# A1 & A4 & Z1 & Z2 & Z3 & Z4
# A1 & !A4 & Z1 & Z2 & Z3 & !Z4
# A1 & A2 & A3 & !A4 & Z1 & !Z4
# A1 & A2 & !Z1 & !Z2 & Z3 & Z4;
-- Node name is '~850~3' from file "chengfa.tdf" line 44, column 9
-- Equation name is '~850~3', location is LC048, type is buried.
-- synthesized logic cell
_LC048 = LCELL( _EQ020 $ GND);
_EQ020 = A1 & !A2 & !A3 & A4 & Z1 & Z4
# A1 & A4 & Z1 & !Z2 & !Z3 & Z4
# !A1 & A2 & A3 & !Z1 & Z2 & Z3
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