📄 xinjieguo.rpt
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Logic Array Block 'F':
Logic cells placed in LAB 'F'
+--------- LC83 LEDB3
| +------- LC85 LEDB4
| | +----- LC88 LEDB5
| | | +--- LC86 LEDB6
| | | | +- LC91 LEDB7
| | | | |
| | | | | Other LABs fed by signals
| | | | | that feed LAB 'F'
LC | | | | | | A B C D E F G H | Logic cells that feed LAB 'F':
Pin
84 -> * * * * * | * * - * * * - * | <-- LOA
83 -> * * * * * | * * - * * * - * | <-- LOB
LC?? -> * * * - - | - - - - * * - - | <-- |chengfa:19|~545~1
LC?? -> * - * * - | - - - - * * - - | <-- |chengfa:19|~598~1
LC?? -> * * - * - | - - - - * * - - | <-- |chengfa:19|~600~1
LC?? -> * * * * - | - - - - * * - - | <-- |chengfa:19|~610~1
LC?? -> * * * * - | - - - - * * - - | <-- |chengfa:19|~620~1
LC?? -> * - - * - | - - - - * * - - | <-- |chengfa:19|~673~1
LC?? -> * - - * - | - - - - * * - - | <-- |chengfa:19|~675~1
LC?? -> * * * * - | - - - - * * - - | <-- |chengfa:19|~685~1
LC?? -> * * * * - | - - - - * * - - | <-- |chengfa:19|~753~1
LC?? -> * * * * - | - - - - * * - - | <-- |chengfa:19|~760~1
LC?? -> * - * * - | - - - - * * - - | <-- |chengfa:19|~828~1
LC?? -> * - * * - | - - - - * * - - | <-- |chengfa:19|~835~1
LC?? -> * * * * - | - - - - * * - * | <-- |xianshi:21|~505~1
LC?? -> - - - - * | - - - - - * - - | <-- |xianshi:21|~522~1
LC?? -> - - - - * | - - - - - * - - | <-- |xianshi:21|~522~2
LC?? -> - - - - * | - - - - - * - - | <-- |xianshi:21|~522~3
LC?? -> - - - - * | - - - - - * - - | <-- |xianshi:21|~522~4
LC?? -> - - - - * | - - - - - * - - | <-- |xianshi:21|~522~5
LC?? -> - - - - * | - - - - - * - - | <-- |xianshi:21|~522~6
LC?? -> - - - - * | - - - - - * - - | <-- |xianshi:21|~522~7
LC?? -> - - - - * | - - - - - * - - | <-- |xianshi:21|~522~8
LC?? -> * - - - - | - - - - - * - - | <-- |xianshi:21|~527~1
LC?? -> - * - - - | - - - - - * - - | <-- |xianshi:21|~528~1
LC?? -> - * - - - | - - - - - * - - | <-- |xianshi:21|~528~2
LC?? -> - * - - - | - - - - - * - - | <-- |xianshi:21|~528~3
LC?? -> - * - - - | - - - - - * - - | <-- |xianshi:21|~528~4
LC?? -> - * - - - | - - - - - * - - | <-- |xianshi:21|~528~5
LC?? -> - * - - - | - - - - - * - - | <-- |xianshi:21|~528~6
LC?? -> - * - - - | - - - - - * - - | <-- |xianshi:21|~528~7
LC?? -> - * * - - | - - - - - * - - | <-- |xianshi:21|~528~8
LC?? -> - - * - - | - - - - - * - - | <-- |xianshi:21|~529~1
LC?? -> - - - * - | - - - - - * - - | <-- |xianshi:21|~530~1
LC?? -> - - - * - | - - - - - * - - | <-- |xianshi:21|~530~2
LC?? -> - - - * - | - - - - - * - - | <-- |xianshi:21|~530~3
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\baowenlei\xinjieguo.rpt
xinjieguo
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'G':
Logic cells placed in LAB 'G'
+- LC109 LEDC2
|
| Other LABs fed by signals
| that feed LAB 'G'
LC | | A B C D E F G H | Logic cells that feed LAB 'G':
Pin
84 -> - | * * - * * * - * | <-- LOA
83 -> - | * * - * * * - * | <-- LOB
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\baowenlei\xinjieguo.rpt
xinjieguo
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'H':
Logic cells placed in LAB 'H'
+----------- LC115 LEDC1
| +--------- LC118 LEDC3
| | +------- LC120 LEDC4
| | | +----- LC126 LEDC5
| | | | +--- LC123 LEDC6
| | | | | +- LC125 LEDC7
| | | | | |
| | | | | | Other LABs fed by signals
| | | | | | that feed LAB 'H'
LC | | | | | | | A B C D E F G H | Logic cells that feed LAB 'H':
Pin
84 -> - - - - - * | * * - * * * - * | <-- LOA
83 -> - - - - - * | * * - * * * - * | <-- LOB
LC?? -> - - - - - * | - - - - - - - * | <-- |fuhao:18|~33~1
LC?? -> - - - - - * | * - - - - - - * | <-- |shuru:20|FF5
LC?? -> - - - - - * | * - - - - - - * | <-- |shuru:20|FF10
LC?? -> - - - - - * | - - - - * * - * | <-- |xianshi:21|~505~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\baowenlei\xinjieguo.rpt
xinjieguo
** EQUATIONS **
LOA : INPUT;
LOB : INPUT;
XIE0 : INPUT;
XIE1 : INPUT;
XIE2 : INPUT;
XIE3 : INPUT;
XIE4 : INPUT;
-- Node name is 'C0'
-- Equation name is 'C0', type is output
C0 = LCELL( _EQ001 $ VCC);
_EQ001 = _X001 & _X002;
_X001 = EXP( LOA & !LOB & _N034);
_X002 = EXP(!LOA & LOB & _N034);
-- Node name is 'C1'
-- Equation name is 'C1', type is output
C1 = LCELL( _EQ002 $ GND);
_EQ002 = !LOA & LOB & _N046
# LOA & !LOB & _N046;
-- Node name is 'C2'
-- Equation name is 'C2', type is output
C2 = LCELL( _EQ003 $ GND);
_EQ003 = !LOA & LOB & _N044
# LOA & !LOB & _N044;
-- Node name is 'C3'
-- Equation name is 'C3', type is output
C3 = LCELL( _EQ004 $ GND);
_EQ004 = !LOA & LOB & _N042
# LOA & !LOB & _N042;
-- Node name is 'C4'
-- Equation name is 'C4', type is output
C4 = LCELL( _EQ005 $ GND);
_EQ005 = !LOA & LOB & _N040
# LOA & !LOB & _N040;
-- Node name is 'C5'
-- Equation name is 'C5', type is output
C5 = LCELL( _EQ006 $ VCC);
_EQ006 = _X003 & _X004;
_X003 = EXP(!LOA & !LOB & _N033);
_X004 = EXP( LOA & !LOB & _N033);
-- Node name is 'C6'
-- Equation name is 'C6', type is output
C6 = LCELL( _EQ007 $ GND);
_EQ007 = !LOB & _N039;
-- Node name is 'C7'
-- Equation name is 'C7', type is output
C7 = LCELL( _EQ008 $ GND);
_EQ008 = !LOB & _N038;
-- Node name is 'C8'
-- Equation name is 'C8', type is output
C8 = LCELL( _EQ009 $ GND);
_EQ009 = !LOB & _N049;
-- Node name is 'C9'
-- Equation name is 'C9', type is output
C9 = LCELL( _EQ010 $ GND);
_EQ010 = !LOB & _N048;
-- Node name is 'LEDA1'
-- Equation name is 'LEDA1', type is output
LEDA1 = LCELL( _EQ011 $ !_N067);
_EQ011 = LOA & !LOB & _N039 & _N046 & _N067 & _N068 & _N076 & _X005
# LOA & !LOB & _N039 & _N046 & _N067 & _N068 & _N074 & !_N076
# LOA & !LOB & _N039 & _N046 & _N067 & _N068 & !_N074 & _N076
# LOA & !LOB & _N067 & !_N068 & _N074 & !_N076 & _X006;
_X005 = EXP( LOA & !LOB);
_X006 = EXP( LOA & !LOB & _N039 & _N046);
-- Node name is 'LEDA2'
-- Equation name is 'LEDA2', type is output
LEDA2 = LCELL( _EQ012 $ !_N075);
_EQ012 = LOA & !LOB & _N039 & _N046 & !_N068 & _N074 & _N075 & !_N076
# LOA & !LOB & _N039 & _N046 & _N068 & _N075 & _N076
# LOA & !LOB & _N074 & _N075 & _N076 & _X006;
_X006 = EXP( LOA & !LOB & _N039 & _N046);
-- Node name is 'LEDA3'
-- Equation name is 'LEDA3', type is output
LEDA3 = LCELL( _EQ013 $ !_N075);
_EQ013 = LOA & !LOB & _N068 & _N074 & _N075 & _N076
# !_N068 & !_N074 & _N075 & _N076 & _X006
# !_N068 & _N075 & _N076 & _X005 & _X006;
_X006 = EXP( LOA & !LOB & _N039 & _N046);
_X005 = EXP( LOA & !LOB);
-- Node name is 'LEDA4'
-- Equation name is 'LEDA4', type is output
LEDA4 = LCELL( _EQ014 $ _EQ015);
_EQ014 = LOA & !LOB & _N039 & _N046 & _N067 & _N073 & _N074 & !_N076 &
!_N126 & _X007 & _X008
# LOA & !LOB & _N067 & _N073 & _N074 & _N076 & !_N126 & _X006 &
_X007 & _X008;
_X007 = EXP( LOA & !LOB & _N039 & _N046 & _N067 & !_N068 & _N073);
_X008 = EXP( LOA & !LOB & _N039 & _N046 & _N067 & _N073 & !_N074 & _N076);
_X006 = EXP( LOA & !LOB & _N039 & _N046);
_EQ015 = !_N126 & _X007 & _X008;
_X007 = EXP( LOA & !LOB & _N039 & _N046 & _N067 & !_N068 & _N073);
_X008 = EXP( LOA & !LOB & _N039 & _N046 & _N067 & _N073 & !_N074 & _N076);
-- Node name is 'LEDA5'
-- Equation name is 'LEDA5', type is output
LEDA5 = LCELL( _EQ016 $ _EQ017);
_EQ016 = LOA & !LOB & _N039 & _N046 & _N067 & _N068 & _N073 & _N076
# LOA & !LOB & _N067 & _N073 & _N074 & _X009
# _N067 & _N068 & _N073 & !_N076 & _X006
# _N067 & !_N068 & _N073 & _N076 & _X006;
_X009 = EXP(!_N068 & !_N076);
_X006 = EXP( LOA & !LOB & _N039 & _N046);
_EQ017 = _X010 & _X011 & _X012;
_X010 = EXP( LOB & _N067 & !_N068 & _N073 & !_N076);
_X011 = EXP( _N067 & !_N068 & _N073 & !_N074 & !_N076);
_X012 = EXP(!LOA & _N067 & !_N068 & _N073 & !_N076);
-- Node name is 'LEDA6'
-- Equation name is 'LEDA6', type is output
LEDA6 = LCELL( _EQ018 $ !_N073);
_EQ018 = LOA & !LOB & _N039 & _N046 & _N068 & _N073 & _N074 & !_N076
# !_N068 & _N073 & !_N074 & _N076
# !_N068 & _N073 & _N076 & _X005
# !_N067 & _N073;
_X005 = EXP( LOA & !LOB);
-- Node name is 'LEDA7'
-- Equation name is 'LEDA7', type is output
LEDA7 = LCELL( _EQ019 $ VCC);
_EQ019 = LOA & !LOB & _N039 & _N046 & _N067 & _N073 & _N075
# LOA & !LOB & _N067 & _N073 & _N074 & _N075
# _N067 & _N068 & _N073 & _N075
# _N067 & _N073 & _N075 & _N076;
-- Node name is 'LEDB1'
-- Equation name is 'LEDB1', type is output
LEDB1 = LCELL( _EQ020 $ _EQ021);
_EQ020 = _N036 & !_N052 & !_N056 & _N058 & !_N062 & !_N063 & !_N064 &
!_N098 & !_N099 & !_N118 & !_N137 & _X013 & _X014 & _X015 &
_X016
# _N036 & !_N052 & !_N056 & _N059 & !_N062 & !_N063 & !_N064 &
!_N098 & !_N099 & !_N118 & !_N137 & _X013 & _X014 & _X015 &
_X016
# _N036 & _N051 & !_N052 & !_N056 & _N058 & !_N064 & !_N098 &
!_N099 & !_N118 & !_N137 & _X013 & _X014 & _X015 & _X016
# _N036 & _N051 & !_N052 & !_N056 & _N059 & !_N064 & !_N098 &
!_N099 & !_N118 & !_N137 & _X013 & _X014 & _X015 & _X016;
_X013 = EXP( LOB & _N036);
_X014 = EXP(!LOA & _N036);
_X015 = EXP( _N036 & !_N050 & !_N052 & !_N056 & !_N060 & !_N061);
_X016 = EXP( _N036 & _N037 & !_N050 & !_N052 & !_N056);
_EQ021 = !_N098 & !_N099 & !_N118 & !_N137 & _X013 & _X014 & _X015 &
_X016;
_X013 = EXP( LOB & _N036);
_X014 = EXP(!LOA & _N036);
_X015 = EXP( _N036 & !_N050 & !_N052 & !_N056 & !_N060 & !_N061);
_X016 = EXP( _N036 & _N037 & !_N050 & !_N052 & !_N056);
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