📄 xinjieguo.rpt
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- ?? ?? SOFT s t 2 0 1 2 7 7 3 |chengfa:19|~453~1
- ?? ?? SOFT s t 1 0 1 0 6 0 1 |chengfa:19|~453~2
- ?? ?? SOFT s t 4 1 1 2 14 0 2 |chengfa:19|~526~1
- ?? ?? SOFT s t 1 0 1 0 8 0 1 |chengfa:19|~526~2
- ?? ?? SOFT s t 1 0 1 0 8 0 1 |chengfa:19|~526~3
- ?? ?? SOFT s t 1 0 1 0 8 0 1 |chengfa:19|~526~4
- ?? ?? SOFT s t 1 0 1 0 8 0 1 |chengfa:19|~526~5
- ?? ?? SOFT s t 1 0 1 0 7 0 1 |chengfa:19|~526~6
- ?? ?? SOFT s t 1 0 1 0 8 0 1 |chengfa:19|~526~7
- ?? ?? SOFT s t 4 3 1 2 9 0 1 |chengfa:19|~530~1
- ?? ?? SOFT s t 1 0 1 2 8 0 1 |chengfa:19|~530~2
- ?? ?? SOFT s t 4 2 1 2 7 0 1 |chengfa:19|~532~1
- ?? ?? SOFT s t 1 0 1 0 6 0 1 |chengfa:19|~532~2
- ?? ?? SOFT s t 7 6 1 2 10 5 43 |chengfa:19|~545~1
- ?? ?? SOFT s t 1 0 1 0 8 0 1 |chengfa:19|~545~2
- ?? ?? SOFT s t 0 0 0 0 8 0 1 |chengfa:19|~545~3
- ?? ?? SOFT s t 6 1 1 2 8 5 20 |chengfa:19|~598~1
- ?? ?? SOFT s t 3 0 1 2 9 5 23 |chengfa:19|~600~1
- ?? ?? SOFT s t 1 0 1 0 6 0 1 |chengfa:19|~600~2
- ?? ?? SOFT s t 5 0 1 2 12 6 23 |chengfa:19|~610~1
- ?? ?? SOFT s t 1 0 1 0 8 0 1 |chengfa:19|~610~2
- ?? ?? SOFT s t 1 0 1 0 8 0 1 |chengfa:19|~610~3
- ?? ?? SOFT s t 1 0 1 0 8 0 1 |chengfa:19|~610~4
- ?? ?? SOFT s t 2 1 0 2 11 6 28 |chengfa:19|~620~1
- ?? ?? SOFT s t 1 0 1 2 9 0 1 |chengfa:19|~620~2
- ?? ?? SOFT s t 1 0 1 2 9 0 1 |chengfa:19|~620~3
- ?? ?? SOFT s t 1 0 1 2 9 0 1 |chengfa:19|~620~4
- ?? ?? SOFT s t 0 0 0 2 6 0 3 |chengfa:19|~636~1
- ?? ?? SOFT s t 5 4 1 2 6 0 10 |chengfa:19|~661~1
- ?? ?? SOFT s t 7 4 1 2 8 4 25 |chengfa:19|~673~1
- ?? ?? SOFT s t 0 0 0 2 8 4 26 |chengfa:19|~675~1
- ?? ?? SOFT s t 1 1 0 2 11 6 23 |chengfa:19|~685~1
- ?? ?? SOFT s t 1 0 1 2 9 0 2 |chengfa:19|~685~2
- ?? ?? SOFT s t 1 0 1 2 9 0 2 |chengfa:19|~685~3
- ?? ?? SOFT s t 1 0 1 2 9 0 2 |chengfa:19|~685~4
- ?? ?? SOFT s t 0 0 0 2 8 0 2 |chengfa:19|~685~5
- ?? ?? SOFT s t 1 1 0 2 10 0 1 |chengfa:19|~694~1
- ?? ?? SOFT s t 0 0 0 2 6 0 4 |chengfa:19|~736~1
- ?? ?? SOFT s t 2 1 1 2 17 6 25 |chengfa:19|~753~1
- ?? ?? SOFT s t 0 0 0 2 9 6 25 |chengfa:19|~760~1
- ?? ?? SOFT s t 2 2 0 2 17 5 25 |chengfa:19|~828~1
- ?? ?? SOFT s t 4 3 1 2 17 5 24 |chengfa:19|~835~1
- ?? ?? SOFT s t 1 0 1 2 10 0 4 |chengfa:19|~835~2
- ?? ?? SOFT s t 1 0 1 2 10 0 4 |chengfa:19|~835~3
- ?? ?? SOFT s t 1 0 1 2 10 0 4 |chengfa:19|~835~4
- ?? ?? SOFT s t 1 0 1 2 8 0 4 |chengfa:19|~835~5
- ?? ?? SOFT s t 1 0 1 2 9 0 4 |chengfa:19|~835~6
- ?? ?? SOFT s t 0 0 0 2 2 0 1 |chengfa:19|~847~1
- ?? ?? SOFT s t 0 0 0 2 4 7 1 |chengfa:19|~848~1
- ?? ?? SOFT s t 0 0 0 2 10 7 3 |chengfa:19|~850~1
- ?? ?? SOFT s t 0 0 0 2 2 1 1 |fuhao:18|~33~1
- ?? ?? LCELL t 0 0 0 2 1 0 3 |shuru:20|FF0
- ?? ?? LCELL t 0 0 0 2 1 0 3 |shuru:20|FF1
- ?? ?? LCELL t 0 0 0 2 1 0 3 |shuru:20|FF2
- ?? ?? LCELL t 0 0 0 2 1 0 3 |shuru:20|FF3
- ?? ?? LCELL t 0 0 0 2 1 0 3 |shuru:20|FF4
- ?? ?? LCELL s t 0 0 0 3 2 0 1 |shuru:20|FF5~1
- ?? ?? LCELL t 1 0 1 3 3 2 4 |shuru:20|FF5
- ?? ?? LCELL s t 0 0 0 3 2 0 1 |shuru:20|FF6~1
- ?? ?? LCELL t 1 0 1 3 3 8 53 |shuru:20|FF6
- ?? ?? LCELL s t 0 0 0 3 2 0 1 |shuru:20|FF7~1
- ?? ?? LCELL t 1 0 1 3 3 1 55 |shuru:20|FF7
- ?? ?? LCELL s t 0 0 0 3 2 0 1 |shuru:20|FF8~1
- ?? ?? LCELL t 1 0 1 3 3 1 52 |shuru:20|FF8
- ?? ?? LCELL s t 0 0 0 3 2 0 1 |shuru:20|FF9~1
- ?? ?? LCELL t 1 0 1 3 3 1 47 |shuru:20|FF9
- ?? ?? LCELL t 0 0 0 2 1 2 4 |shuru:20|FF10
- ?? ?? LCELL t 0 0 0 2 1 8 52 |shuru:20|FF11
- ?? ?? LCELL t 0 0 0 2 1 1 50 |shuru:20|FF12
- ?? ?? LCELL t 0 0 0 2 1 1 48 |shuru:20|FF13
- ?? ?? LCELL t 0 0 0 2 1 1 42 |shuru:20|FF14
- ?? ?? SOFT s t 0 0 0 2 1 0 1 |shuru:20|~110~1
- ?? ?? SOFT s t 0 0 0 2 1 0 1 |shuru:20|~163~1
- ?? ?? SOFT s t 0 0 0 2 7 5 1 |xianshi:21|~72~1
- ?? ?? SOFT s t 0 0 0 2 6 4 1 |xianshi:21|~125~1
- ?? ?? SOFT s t 0 0 0 2 7 3 0 |xianshi:21|~170~1
- ?? ?? SOFT s t 2 1 1 2 8 1 0 |xianshi:21|~209~1
- ?? ?? SOFT s t 2 1 1 2 23 7 13 |xianshi:21|~505~1
- ?? ?? SOFT s t 1 0 1 0 12 1 0 |xianshi:21|~522~1
- ?? ?? SOFT s t 1 0 1 0 10 1 0 |xianshi:21|~522~2
- ?? ?? SOFT s t 1 0 1 0 11 1 0 |xianshi:21|~522~3
- ?? ?? SOFT s t 1 0 1 0 12 1 0 |xianshi:21|~522~4
- ?? ?? SOFT s t 1 0 1 0 10 1 0 |xianshi:21|~522~5
- ?? ?? SOFT s t 1 0 1 0 11 1 0 |xianshi:21|~522~6
- ?? ?? SOFT s t 1 0 1 0 9 1 0 |xianshi:21|~522~7
- ?? ?? SOFT s t 0 0 0 2 10 1 0 |xianshi:21|~522~8
- ?? ?? SOFT s t 1 0 1 0 9 1 0 |xianshi:21|~525~1
- ?? ?? SOFT s t 1 0 1 0 10 1 0 |xianshi:21|~525~2
- ?? ?? SOFT s t 1 0 1 0 10 1 0 |xianshi:21|~525~3
- ?? ?? SOFT s t 0 0 0 0 8 1 0 |xianshi:21|~525~4
- ?? ?? SOFT s t 1 0 1 0 10 1 0 |xianshi:21|~526~1
- ?? ?? SOFT s t 1 0 1 0 10 1 0 |xianshi:21|~526~2
- ?? ?? SOFT s t 1 0 1 0 11 1 0 |xianshi:21|~526~3
- ?? ?? SOFT s t 1 0 1 0 12 1 0 |xianshi:21|~526~4
- ?? ?? SOFT s t 1 0 1 0 11 1 0 |xianshi:21|~527~1
- ?? ?? SOFT s t 1 0 1 2 12 1 0 |xianshi:21|~528~1
- ?? ?? SOFT s t 1 0 1 2 12 1 0 |xianshi:21|~528~2
- ?? ?? SOFT s t 1 0 1 2 10 1 0 |xianshi:21|~528~3
- ?? ?? SOFT s t 1 0 1 2 11 1 0 |xianshi:21|~528~4
- ?? ?? SOFT s t 1 0 1 2 8 1 0 |xianshi:21|~528~5
- ?? ?? SOFT s t 1 0 1 2 8 1 0 |xianshi:21|~528~6
- ?? ?? SOFT s t 1 0 1 2 9 1 0 |xianshi:21|~528~7
- ?? ?? SOFT s t 1 0 1 2 10 2 0 |xianshi:21|~528~8
- ?? ?? SOFT s t 1 0 1 2 10 1 0 |xianshi:21|~529~1
- ?? ?? SOFT s t 1 0 1 0 13 1 0 |xianshi:21|~530~1
- ?? ?? SOFT s t 1 0 1 0 11 1 0 |xianshi:21|~530~2
- ?? ?? SOFT s t 0 0 0 0 7 1 0 |xianshi:21|~530~3
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\baowenlei\xinjieguo.rpt
xinjieguo
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+----- LC16 C0
| +--- LC3 C4
| | +- LC14 C5
| | |
| | | Other LABs fed by signals
| | | that feed LAB 'A'
LC | | | | A B C D E F G H | Logic cells that feed LAB 'A':
Pin
84 -> * * * | * * - * * * - * | <-- LOA
83 -> * * * | * * - * * * - * | <-- LOB
LC?? -> * - - | * - - - - - - * | <-- |shuru:20|FF5
LC?? -> - * - | * - - - - - - - | <-- |shuru:20|FF9
LC?? -> - - * | * - - - - - - * | <-- |shuru:20|FF10
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\baowenlei\xinjieguo.rpt
xinjieguo
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------- LC21 C1
| +----------- LC17 C2
| | +--------- LC19 C3
| | | +------- LC24 C6
| | | | +----- LC29 C7
| | | | | +--- LC27 C8
| | | | | | +- LC25 C9
| | | | | | |
| | | | | | | Other LABs fed by signals
| | | | | | | that feed LAB 'B'
LC | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'B':
Pin
84 -> * * * - - - - | * * - * * * - * | <-- LOA
83 -> * * * * * * * | * * - * * * - * | <-- LOB
LC?? -> * - - - - - - | - * - * * - - - | <-- |shuru:20|FF6
LC?? -> - * - - - - - | - * - - - - - - | <-- |shuru:20|FF7
LC?? -> - - * - - - - | - * - - - - - - | <-- |shuru:20|FF8
LC?? -> - - - * - - - | - * - * * - - - | <-- |shuru:20|FF11
LC?? -> - - - - * - - | - * - - - - - - | <-- |shuru:20|FF12
LC?? -> - - - - - * - | - * - - - - - - | <-- |shuru:20|FF13
LC?? -> - - - - - - * | - * - - - - - - | <-- |shuru:20|FF14
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\baowenlei\xinjieguo.rpt
xinjieguo
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+--- LC49 LEDA1
| +- LC51 LEDA2
| |
| | Other LABs fed by signals
| | that feed LAB 'D'
LC | | | A B C D E F G H | Logic cells that feed LAB 'D':
Pin
84 -> * * | * * - * * * - * | <-- LOA
83 -> * * | * * - * * * - * | <-- LOB
LC?? -> * * | - - - * * - - - | <-- |chengfa:19|~453~1
LC?? -> * * | - - - * * - - - | <-- |chengfa:19|~848~1
LC?? -> * * | - - - * * - - - | <-- |chengfa:19|~850~1
LC?? -> * * | - * - * * - - - | <-- |shuru:20|FF6
LC?? -> * * | - * - * * - - - | <-- |shuru:20|FF11
LC?? -> * - | - - - * * - - - | <-- |xianshi:21|~72~1
LC?? -> - * | - - - * * - - - | <-- |xianshi:21|~170~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\baowenlei\xinjieguo.rpt
xinjieguo
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'E':
Logic cells placed in LAB 'E'
+------------- LC65 LEDA3
| +----------- LC67 LEDA4
| | +--------- LC72 LEDA5
| | | +------- LC69 LEDA6
| | | | +----- LC73 LEDA7
| | | | | +--- LC80 LEDB1
| | | | | | +- LC75 LEDB2
| | | | | | |
| | | | | | | Other LABs fed by signals
| | | | | | | that feed LAB 'E'
LC | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'E':
Pin
84 -> * * * * * * * | * * - * * * - * | <-- LOA
83 -> * * * * * * * | * * - * * * - * | <-- LOB
LC?? -> * * * * * - - | - - - * * - - - | <-- |chengfa:19|~453~1
LC?? -> - - - - - * * | - - - - * * - - | <-- |chengfa:19|~545~1
LC?? -> - - - - - * * | - - - - * * - - | <-- |chengfa:19|~598~1
LC?? -> - - - - - * * | - - - - * * - - | <-- |chengfa:19|~600~1
LC?? -> - - - - - * * | - - - - * * - - | <-- |chengfa:19|~610~1
LC?? -> - - - - - * * | - - - - * * - - | <-- |chengfa:19|~620~1
LC?? -> - - - - - * * | - - - - * * - - | <-- |chengfa:19|~673~1
LC?? -> - - - - - * * | - - - - * * - - | <-- |chengfa:19|~675~1
LC?? -> - - - - - * * | - - - - * * - - | <-- |chengfa:19|~685~1
LC?? -> - - - - - * * | - - - - * * - - | <-- |chengfa:19|~753~1
LC?? -> - - - - - * * | - - - - * * - - | <-- |chengfa:19|~760~1
LC?? -> - - - - - * * | - - - - * * - - | <-- |chengfa:19|~828~1
LC?? -> - - - - - * * | - - - - * * - - | <-- |chengfa:19|~835~1
LC?? -> * * * * * - - | - - - * * - - - | <-- |chengfa:19|~848~1
LC?? -> * * * * * - - | - - - * * - - - | <-- |chengfa:19|~850~1
LC?? -> * * * * * - - | - * - * * - - - | <-- |shuru:20|FF6
LC?? -> * * * * * - - | - * - * * - - - | <-- |shuru:20|FF11
LC?? -> - * * * * - - | - - - * * - - - | <-- |xianshi:21|~72~1
LC?? -> - * * * * - - | - - - - * - - - | <-- |xianshi:21|~125~1
LC?? -> * - - - * - - | - - - * * - - - | <-- |xianshi:21|~170~1
LC?? -> - * - - - - - | - - - - * - - - | <-- |xianshi:21|~209~1
LC?? -> - - - - - * * | - - - - * * - * | <-- |xianshi:21|~505~1
LC?? -> - - - - - * - | - - - - * - - - | <-- |xianshi:21|~525~1
LC?? -> - - - - - * - | - - - - * - - - | <-- |xianshi:21|~525~2
LC?? -> - - - - - * - | - - - - * - - - | <-- |xianshi:21|~525~3
LC?? -> - - - - - * - | - - - - * - - - | <-- |xianshi:21|~525~4
LC?? -> - - - - - - * | - - - - * - - - | <-- |xianshi:21|~526~1
LC?? -> - - - - - - * | - - - - * - - - | <-- |xianshi:21|~526~2
LC?? -> - - - - - - * | - - - - * - - - | <-- |xianshi:21|~526~3
LC?? -> - - - - - - * | - - - - * - - - | <-- |xianshi:21|~526~4
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\baowenlei\xinjieguo.rpt
xinjieguo
** LOGIC CELL INTERCONNECTIONS **
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