prev_cmp_crcsend.map.qmsg

用vhdl代码实现循环冗余检验

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.0 Build 215 05/29/2008 SJ Full Version " "Info: Version 8.0 Build 215 05/29/2008 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon May 04 22:15:19 2009 " "Info: Processing started: Mon May 04 22:15:19 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off crcsend -c crcsend " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off crcsend -c crcsend" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "crcsend.vhd 4 2 " "Info: Found 4 design units, including 2 entities, in source file crcsend.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 crcsend-comm " "Info: Found design unit 1: crcsend-comm" {  } { { "crcsend.vhd" "" { Text "D:/mydocument/crcsend/crcsend.vhd" 21 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 crcrec-comm " "Info: Found design unit 2: crcrec-comm" {  } { { "crcsend.vhd" "" { Text "D:/mydocument/crcsend/crcsend.vhd" 89 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 crcsend " "Info: Found entity 1: crcsend" {  } { { "crcsend.vhd" "" { Text "D:/mydocument/crcsend/crcsend.vhd" 9 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "2 crcrec " "Info: Found entity 2: crcrec" {  } { { "crcsend.vhd" "" { Text "D:/mydocument/crcsend/crcsend.vhd" 77 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "downto6 crcsend.vhd(115) " "Error (10482): VHDL error at crcsend.vhd(115): object \"downto6\" is used but not declared" {  } { { "crcsend.vhd" "" { Text "D:/mydocument/crcsend/crcsend.vhd" 115 0 0 } }  } 0 10482 "VHDL error at %2!s!: object \"%1!s!\" is used but not declared" 0 0 "" 0 0}
{ "Error" "EVRFX_VHDL_ERROR_INDEXED_NAME_TYPE_MISMATCH" "std_logic_vector crcsend.vhd(115) " "Error (10381): VHDL Type Mismatch error at crcsend.vhd(115): indexed name returns a value whose type does not match \"std_logic_vector\", the type of the target expression" {  } { { "crcsend.vhd" "" { Text "D:/mydocument/crcsend/crcsend.vhd" 115 0 0 } }  } 0 10381 "VHDL Type Mismatch error at %2!s!: indexed name returns a value whose type does not match \"%1!s!\", the type of the target expression" 0 0 "" 0 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 2 s 0 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 0 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "209 " "Error: Peak virtual memory: 209 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Error" "EQEXE_END_BANNER_TIME" "Mon May 04 22:15:21 2009 " "Error: Processing ended: Mon May 04 22:15:21 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:02 " "Error: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Error: Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}