prev_cmp_crcsend.qmsg

用vhdl代码实现循环冗余检验

{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off crcsend -c crcsend " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off crcsend -c crcsend" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" {  } {  } 0 0 "Assembler is generating device programming files" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "187 " "Info: Peak virtual memory: 187 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon May 04 22:18:21 2009 " "Info: Processing ended: Mon May 04 22:18:21 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.0 Build 215 05/29/2008 SJ Full Version " "Info: Version 8.0 Build 215 05/29/2008 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon May 04 22:18:22 2009 " "Info: Processing started: Mon May 04 22:18:22 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off crcsend -c crcsend --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off crcsend -c crcsend --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node \"CLK\" is an undefined clock" {  } { { "crcsend.vhd" "" { Text "D:/mydocument/crcsend/crcsend.vhd" 13 -1 0 } } { "d:/tools/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/tools/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register cnt\[0\] register dtemp\[7\] 228.1 MHz 4.384 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 228.1 MHz between source register \"cnt\[0\]\" and destination register \"dtemp\[7\]\" (period= 4.384 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.123 ns + Longest register register " "Info: + Longest register to register delay is 4.123 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt\[0\] 1 REG LC_X6_Y15_N0 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y15_N0; Fanout = 5; REG Node = 'cnt\[0\]'" {  } { { "d:/tools/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt[0] } "NODE_NAME" } } { "crcsend.vhd" "" { Text "D:/mydocument/crcsend/crcsend.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.548 ns) + CELL(0.442 ns) 0.990 ns process0~140 2 COMB LC_X6_Y15_N6 3 " "Info: 2: + IC(0.548 ns) + CELL(0.442 ns) = 0.990 ns; Loc. = LC_X6_Y15_N6; Fanout = 3; COMB Node = 'process0~140'" {  } { { "d:/tools/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.990 ns" { cnt[0] process0~140 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.433 ns) + CELL(0.114 ns) 1.537 ns LessThan0~56 3 COMB LC_X6_Y15_N5 2 " "Info: 3: + IC(0.433 ns) + CELL(0.114 ns) = 1.537 ns; Loc. = LC_X6_Y15_N5; Fanout = 2; COMB Node = 'LessThan0~56'" {  } { { "d:/tools/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.547 ns" { process0~140 LessThan0~56 } "NODE_NAME" } } { "d:/tools/altera/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/tools/altera/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1509 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.466 ns) + CELL(0.114 ns) 2.117 ns dtemp\[7\]~856 4 COMB LC_X6_Y15_N9 11 " "Info: 4: + IC(0.466 ns) + CELL(0.114 ns) = 2.117 ns; Loc. = LC_X6_Y15_N9; Fanout = 11; COMB Node = 'dtemp\[7\]~856'" {  } { { "d:/tools/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.580 ns" { LessThan0~56 dtemp[7]~856 } "NODE_NAME" } } { "crcsend.vhd" "" { Text "D:/mydocument/crcsend/crcsend.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.139 ns) + CELL(0.867 ns) 4.123 ns dtemp\[7\] 5 REG LC_X7_Y15_N3 2 " "Info: 5: + IC(1.139 ns) + CELL(0.867 ns) = 4.123 ns; Loc. = LC_X7_Y15_N3; Fanout = 2; REG Node = 'dtemp\[7\]'" {  } { { "d:/tools/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.006 ns" { dtemp[7]~856 dtemp[7] } "NODE_NAME" } } { "crcsend.vhd" "" { Text "D:/mydocument/crcsend/crcsend.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.537 ns ( 37.28 % ) " "Info: Total cell delay = 1.537 ns ( 37.28 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.586 ns ( 62.72 % ) " "Info: Total interconnect delay = 2.586 ns ( 62.72 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/tools/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus/bin/TimingClosureFloorplan.fld" "" "4.123 ns" { cnt[0] process0~140 LessThan0~56 dtemp[7]~856 dtemp[7] } "NODE_NAME" } } { "d:/tools/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/tools/altera/quartus/bin/Technology_Viewer.qrui" "4.123 ns" { cnt[0] {} process0~140 {} LessThan0~56 {} dtemp[7]~856 {} dtemp[7] {} } { 0.000ns 0.548ns 0.433ns 0.466ns 1.139ns } { 0.000ns 0.442ns 0.114ns 0.114ns 0.867ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.954 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_29 48 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 48; CLK Node = 'CLK'" {  } { { "d:/tools/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "crcsend.vhd" "" { Text "D:/mydocument/crcsend/crcsend.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns dtemp\[7\] 2 REG LC_X7_Y15_N3 2 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X7_Y15_N3; Fanout = 2; REG Node = 'dtemp\[7\]'" {  } { { "d:/tools/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.485 ns" { CLK dtemp[7] } "NODE_NAME" } } { "crcsend.vhd" "" { Text "D:/mydocument/crcsend/crcsend.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.80 % ) " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns ( 26.20 % ) " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/tools/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { CLK dtemp[7] } "NODE_NAME" } } { "d:/tools/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/tools/altera/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { CLK {} CLK~out0 {} dtemp[7] {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.954 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_29 48 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 48; CLK Node = 'CLK'" {  } { { "d:/tools/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "crcsend.vhd" "" { Text "D:/mydocument/crcsend/crcsend.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns cnt\[0\] 2 REG LC_X6_Y15_N0 5 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X6_Y15_N0; Fanout = 5; REG Node = 'cnt\[0\]'" {  } { { "d:/tools/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.485 ns" { CLK cnt[0] } "NODE_NAME" } } { "crcsend.vhd" "" { Text "D:/mydocument/crcsend/crcsend.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.80 % ) " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns ( 26.20 % ) " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/tools/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { CLK cnt[0] } "NODE_NAME" } } { "d:/tools/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/tools/altera/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { CLK {} CLK~out0 {} cnt[0] {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "d:/tools/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { CLK dtemp[7] } "NODE_NAME" } } { "d:/tools/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/tools/altera/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { CLK {} CLK~out0 {} dtemp[7] {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/tools/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { CLK cnt[0] } "NODE_NAME" } } { "d:/tools/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/tools/altera/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { CLK {} CLK~out0 {} cnt[0] {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "crcsend.vhd" "" { Text "D:/mydocument/crcsend/crcsend.vhd" 37 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "crcsend.vhd" "" { Text "D:/mydocument/crcsend/crcsend.vhd" 37 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "d:/tools/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus/bin/TimingClosureFloorplan.fld" "" "4.123 ns" { cnt[0] process0~140 LessThan0~56 dtemp[7]~856 dtemp[7] } "NODE_NAME" } } { "d:/tools/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/tools/altera/quartus/bin/Technology_Viewer.qrui" "4.123 ns" { cnt[0] {} process0~140 {} LessThan0~56 {} dtemp[7]~856 {} dtemp[7] {} } { 0.000ns 0.548ns 0.433ns 0.466ns 1.139ns } { 0.000ns 0.442ns 0.114ns 0.114ns 0.867ns } "" } } { "d:/tools/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { CLK dtemp[7] } "NODE_NAME" } } { "d:/tools/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/tools/altera/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { CLK {} CLK~out0 {} dtemp[7] {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/tools/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { CLK cnt[0] } "NODE_NAME" } } { "d:/tools/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/tools/altera/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { CLK {} CLK~out0 {} cnt[0] {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 0}
{ "Info" "ITDB_TSU_RESULT" "dtemp\[7\] datald CLK 7.596 ns register " "Info: tsu for register \"dtemp\[7\]\" (data pin = \"datald\", clock pin = \"CLK\") is 7.596 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.513 ns + Longest pin register " "Info: + Longest pin to register delay is 10.513 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns datald 1 PIN PIN_39 12 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_39; Fanout = 12; PIN Node = 'datald'" {  } { { "d:/tools/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { datald } "NODE_NAME" } } { "crcsend.vhd" "" { Text "D:/mydocument/crcsend/crcsend.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.448 ns) + CELL(0.590 ns) 8.507 ns dtemp\[7\]~856 2 COMB LC_X6_Y15_N9 11 " "Info: 2: + IC(6.448 ns) + CELL(0.590 ns) = 8.507 ns; Loc. = LC_X6_Y15_N9; Fanout = 11; COMB Node = 'dtemp\[7\]~856'" {  } { { "d:/tools/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus/bin/TimingClosureFloorplan.fld" "" "7.038 ns" { datald dtemp[7]~856 } "NODE_NAME" } } { "crcsend.vhd" "" { Text "D:/mydocument/crcsend/crcsend.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.139 ns) + CELL(0.867 ns) 10.513 ns dtemp\[7\] 3 REG LC_X7_Y15_N3 2 " "Info: 3: + IC(1.139 ns) + CELL(0.867 ns) = 10.513 ns; Loc. = LC_X7_Y15_N3; Fanout = 2; REG Node = 'dtemp\[7\]'" {  } { { "d:/tools/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.006 ns" { dtemp[7]~856 dtemp[7] } "NODE_NAME" } } { "crcsend.vhd" "" { Text "D:/mydocument/crcsend/crcsend.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.926 ns ( 27.83 % ) " "Info: Total cell delay = 2.926 ns ( 27.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.587 ns ( 72.17 % ) " "Info: Total interconnect delay = 7.587 ns ( 72.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/tools/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus/bin/TimingClosureFloorplan.fld" "" "10.513 ns" { datald dtemp[7]~856 dtemp[7] } "NODE_NAME" } } { "d:/tools/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/tools/altera/quartus/bin/Technology_Viewer.qrui" "10.513 ns" { datald {} datald~out0 {} dtemp[7]~856 {} dtemp[7] {} } { 0.000ns 0.000ns 6.448ns 1.139ns } { 0.000ns 1.469ns 0.590ns 0.867ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "crcsend.vhd" "" { Text "D:/mydocument/crcsend/crcsend.vhd" 37 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.954 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_29 48 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 48; CLK Node = 'CLK'" {  } { { "d:/tools/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "crcsend.vhd" "" { Text "D:/mydocument/crcsend/crcsend.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns dtemp\[7\] 2 REG LC_X7_Y15_N3 2 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X7_Y15_N3; Fanout = 2; REG Node = 'dtemp\[7\]'" {  } { { "d:/tools/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.485 ns" { CLK dtemp[7] } "NODE_NAME" } } { "crcsend.vhd" "" { Text "D:/mydocument/crcsend/crcsend.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.80 % ) " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns ( 26.20 % ) " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/tools/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { CLK dtemp[7] } "NODE_NAME" } } { "d:/tools/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/tools/altera/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { CLK {} CLK~out0 {} dtemp[7] {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "d:/tools/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus/bin/TimingClosureFloorplan.fld" "" "10.513 ns" { datald dtemp[7]~856 dtemp[7] } "NODE_NAME" } } { "d:/tools/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/tools/altera/quartus/bin/Technology_Viewer.qrui" "10.513 ns" { datald {} datald~out0 {} dtemp[7]~856 {} dtemp[7] {} } { 0.000ns 0.000ns 6.448ns 1.139ns } { 0.000ns 1.469ns 0.590ns 0.867ns } "" } } { "d:/tools/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { CLK dtemp[7] } "NODE_NAME" } } { "d:/tools/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/tools/altera/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { CLK {} CLK~out0 {} dtemp[7] {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK datacrco\[15\] datacrco\[15\]~reg0 8.130 ns register " "Info: tco from clock \"CLK\" to destination pin \"datacrco\[15\]\" through register \"datacrco\[15\]~reg0\" is 8.130 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.954 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_29 48 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 48; CLK Node = 'CLK'" {  } { { "d:/tools/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "crcsend.vhd" "" { Text "D:/mydocument/crcsend/crcsend.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns datacrco\[15\]~reg0 2 REG LC_X6_Y16_N8 1 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X6_Y16_N8; Fanout = 1; REG Node = 'datacrco\[15\]~reg0'" {  } { { "d:/tools/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.485 ns" { CLK datacrco[15]~reg0 } "NODE_NAME" } } { "crcsend.vhd" "" { Text "D:/mydocument/crcsend/crcsend.vhd" 37 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.80 % ) " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns ( 26.20 % ) " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/tools/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { CLK datacrco[15]~reg0 } "NODE_NAME" } } { "d:/tools/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/tools/altera/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { CLK {} CLK~out0 {} datacrco[15]~reg0 {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "crcsend.vhd" "" { Text "D:/mydocument/crcsend/crcsend.vhd" 37 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.952 ns + Longest register pin " "Info: + Longest register to pin delay is 4.952 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns datacrco\[15\]~reg0 1 REG LC_X6_Y16_N8 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y16_N8; Fanout = 1; REG Node = 'datacrco\[15\]~reg0'" {  } { { "d:/tools/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { datacrco[15]~reg0 } "NODE_NAME" } } { "crcsend.vhd" "" { Text "D:/mydocument/crcsend/crcsend.vhd" 37 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.844 ns) + CELL(2.108 ns) 4.952 ns datacrco\[15\] 2 PIN PIN_66 0 " "Info: 2: + IC(2.844 ns) + CELL(2.108 ns) = 4.952 ns; Loc. = PIN_66; Fanout = 0; PIN Node = 'datacrco\[15\]'" {  } { { "d:/tools/altera/