crcsend.fit.qmsg

用vhdl代码实现循环冗余检验

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "3.757 ns register register " "Info: Estimated most critical path is register to register delay of 3.757 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns st 1 REG LAB_X6_Y14 15 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X6_Y14; Fanout = 15; REG Node = 'st'" {  } { { "d:/tools/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { st } "NODE_NAME" } } { "crcsend.vhd" "" { Text "D:/mydocument/crcsend/crcsend.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.297 ns) + CELL(0.114 ns) 1.411 ns process0~141 2 COMB LAB_X5_Y15 1 " "Info: 2: + IC(1.297 ns) + CELL(0.114 ns) = 1.411 ns; Loc. = LAB_X5_Y15; Fanout = 1; COMB Node = 'process0~141'" {  } { { "d:/tools/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.411 ns" { st process0~141 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.361 ns) + CELL(0.292 ns) 2.064 ns process0~3 3 COMB LAB_X5_Y15 2 " "Info: 3: + IC(0.361 ns) + CELL(0.292 ns) = 2.064 ns; Loc. = LAB_X5_Y15; Fanout = 2; COMB Node = 'process0~3'" {  } { { "d:/tools/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.653 ns" { process0~141 process0~3 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.361 ns) + CELL(0.292 ns) 2.717 ns hsend~171 4 COMB LAB_X5_Y15 1 " "Info: 4: + IC(0.361 ns) + CELL(0.292 ns) = 2.717 ns; Loc. = LAB_X5_Y15; Fanout = 1; COMB Node = 'hsend~171'" {  } { { "d:/tools/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.653 ns" { process0~3 hsend~171 } "NODE_NAME" } } { "crcsend.vhd" "" { Text "D:/mydocument/crcsend/crcsend.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.302 ns) + CELL(0.738 ns) 3.757 ns hsend~reg0 5 REG LAB_X4_Y15 2 " "Info: 5: + IC(0.302 ns) + CELL(0.738 ns) = 3.757 ns; Loc. = LAB_X4_Y15; Fanout = 2; REG Node = 'hsend~reg0'" {  } { { "d:/tools/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.040 ns" { hsend~171 hsend~reg0 } "NODE_NAME" } } { "crcsend.vhd" "" { Text "D:/mydocument/crcsend/crcsend.vhd" 37 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.436 ns ( 38.22 % ) " "Info: Total cell delay = 1.436 ns ( 38.22 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.321 ns ( 61.78 % ) " "Info: Total interconnect delay = 2.321 ns ( 61.78 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/tools/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.757 ns" { st process0~141 process0~3 hsend~171 hsend~reg0 } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "1 X0_Y11 X11_Y21 " "Info: Peak interconnect usage is 1% of the available device resources in the region that extends from location X0_Y11 to location X11_Y21" {  } {  } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0 0}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/mydocument/crcsend/crcsend.fit.smsg " "Info: Generated suppressed messages file D:/mydocument/crcsend/crcsend.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "219 " "Info: Peak virtual memory: 219 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon May 04 22:18:15 2009 " "Info: Processing ended: Mon May 04 22:18:15 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Info: Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Info: Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}