📄 mbox_host_reg.h
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#define COUNT_DEC_ADDRESS 0x00000440#define COUNT_DEC_OFFSET 0x00000440#define COUNT_DEC_VALUE_MSB 7#define COUNT_DEC_VALUE_LSB 0#define COUNT_DEC_VALUE_MASK 0x000000ff#define COUNT_DEC_VALUE_GET(x) (((x) & COUNT_DEC_VALUE_MASK) >> COUNT_DEC_VALUE_LSB)#define COUNT_DEC_VALUE_SET(x) (((x) << COUNT_DEC_VALUE_LSB) & COUNT_DEC_VALUE_MASK)#define SCRATCH_ADDRESS 0x00000460#define SCRATCH_OFFSET 0x00000460#define SCRATCH_VALUE_MSB 7#define SCRATCH_VALUE_LSB 0#define SCRATCH_VALUE_MASK 0x000000ff#define SCRATCH_VALUE_GET(x) (((x) & SCRATCH_VALUE_MASK) >> SCRATCH_VALUE_LSB)#define SCRATCH_VALUE_SET(x) (((x) << SCRATCH_VALUE_LSB) & SCRATCH_VALUE_MASK)#define FIFO_TIMEOUT_ADDRESS 0x00000468#define FIFO_TIMEOUT_OFFSET 0x00000468#define FIFO_TIMEOUT_VALUE_MSB 7#define FIFO_TIMEOUT_VALUE_LSB 0#define FIFO_TIMEOUT_VALUE_MASK 0x000000ff#define FIFO_TIMEOUT_VALUE_GET(x) (((x) & FIFO_TIMEOUT_VALUE_MASK) >> FIFO_TIMEOUT_VALUE_LSB)#define FIFO_TIMEOUT_VALUE_SET(x) (((x) << FIFO_TIMEOUT_VALUE_LSB) & FIFO_TIMEOUT_VALUE_MASK)#define FIFO_TIMEOUT_ENABLE_ADDRESS 0x00000469#define FIFO_TIMEOUT_ENABLE_OFFSET 0x00000469#define FIFO_TIMEOUT_ENABLE_SET_MSB 0#define FIFO_TIMEOUT_ENABLE_SET_LSB 0#define FIFO_TIMEOUT_ENABLE_SET_MASK 0x00000001#define FIFO_TIMEOUT_ENABLE_SET_GET(x) (((x) & FIFO_TIMEOUT_ENABLE_SET_MASK) >> FIFO_TIMEOUT_ENABLE_SET_LSB)#define FIFO_TIMEOUT_ENABLE_SET_SET(x) (((x) << FIFO_TIMEOUT_ENABLE_SET_LSB) & FIFO_TIMEOUT_ENABLE_SET_MASK)#define DISABLE_SLEEP_ADDRESS 0x0000046a#define DISABLE_SLEEP_OFFSET 0x0000046a#define DISABLE_SLEEP_FOR_INT_MSB 1#define DISABLE_SLEEP_FOR_INT_LSB 1#define DISABLE_SLEEP_FOR_INT_MASK 0x00000002#define DISABLE_SLEEP_FOR_INT_GET(x) (((x) & DISABLE_SLEEP_FOR_INT_MASK) >> DISABLE_SLEEP_FOR_INT_LSB)#define DISABLE_SLEEP_FOR_INT_SET(x) (((x) << DISABLE_SLEEP_FOR_INT_LSB) & DISABLE_SLEEP_FOR_INT_MASK)#define DISABLE_SLEEP_ON_MSB 0#define DISABLE_SLEEP_ON_LSB 0#define DISABLE_SLEEP_ON_MASK 0x00000001#define DISABLE_SLEEP_ON_GET(x) (((x) & DISABLE_SLEEP_ON_MASK) >> DISABLE_SLEEP_ON_LSB)#define DISABLE_SLEEP_ON_SET(x) (((x) << DISABLE_SLEEP_ON_LSB) & DISABLE_SLEEP_ON_MASK)#define LOCAL_BUS_ENDIAN_ADDRESS 0x0000046e#define LOCAL_BUS_ENDIAN_OFFSET 0x0000046e#define LOCAL_BUS_ENDIAN_BIG_MSB 0#define LOCAL_BUS_ENDIAN_BIG_LSB 0#define LOCAL_BUS_ENDIAN_BIG_MASK 0x00000001#define LOCAL_BUS_ENDIAN_BIG_GET(x) (((x) & LOCAL_BUS_ENDIAN_BIG_MASK) >> LOCAL_BUS_ENDIAN_BIG_LSB)#define LOCAL_BUS_ENDIAN_BIG_SET(x) (((x) << LOCAL_BUS_ENDIAN_BIG_LSB) & LOCAL_BUS_ENDIAN_BIG_MASK)#define LOCAL_BUS_ADDRESS 0x00000470#define LOCAL_BUS_OFFSET 0x00000470#define LOCAL_BUS_SOFT_RESET_MSB 4#define LOCAL_BUS_SOFT_RESET_LSB 4#define LOCAL_BUS_SOFT_RESET_MASK 0x00000010#define LOCAL_BUS_SOFT_RESET_GET(x) (((x) & LOCAL_BUS_SOFT_RESET_MASK) >> LOCAL_BUS_SOFT_RESET_LSB)#define LOCAL_BUS_SOFT_RESET_SET(x) (((x) << LOCAL_BUS_SOFT_RESET_LSB) & LOCAL_BUS_SOFT_RESET_MASK)#define LOCAL_BUS_IO_ENABLE_MSB 3#define LOCAL_BUS_IO_ENABLE_LSB 3#define LOCAL_BUS_IO_ENABLE_MASK 0x00000008#define LOCAL_BUS_IO_ENABLE_GET(x) (((x) & LOCAL_BUS_IO_ENABLE_MASK) >> LOCAL_BUS_IO_ENABLE_LSB)#define LOCAL_BUS_IO_ENABLE_SET(x) (((x) << LOCAL_BUS_IO_ENABLE_LSB) & LOCAL_BUS_IO_ENABLE_MASK)#define LOCAL_BUS_KEEP_AWAKE_MSB 2#define LOCAL_BUS_KEEP_AWAKE_LSB 2#define LOCAL_BUS_KEEP_AWAKE_MASK 0x00000004#define LOCAL_BUS_KEEP_AWAKE_GET(x) (((x) & LOCAL_BUS_KEEP_AWAKE_MASK) >> LOCAL_BUS_KEEP_AWAKE_LSB)#define LOCAL_BUS_KEEP_AWAKE_SET(x) (((x) << LOCAL_BUS_KEEP_AWAKE_LSB) & LOCAL_BUS_KEEP_AWAKE_MASK)#define LOCAL_BUS_STATE_MSB 1#define LOCAL_BUS_STATE_LSB 0#define LOCAL_BUS_STATE_MASK 0x00000003#define LOCAL_BUS_STATE_GET(x) (((x) & LOCAL_BUS_STATE_MASK) >> LOCAL_BUS_STATE_LSB)#define LOCAL_BUS_STATE_SET(x) (((x) << LOCAL_BUS_STATE_LSB) & LOCAL_BUS_STATE_MASK)#define INT_WLAN_ADDRESS 0x00000472#define INT_WLAN_OFFSET 0x00000472#define INT_WLAN_VECTOR_MSB 7#define INT_WLAN_VECTOR_LSB 0#define INT_WLAN_VECTOR_MASK 0x000000ff#define INT_WLAN_VECTOR_GET(x) (((x) & INT_WLAN_VECTOR_MASK) >> INT_WLAN_VECTOR_LSB)#define INT_WLAN_VECTOR_SET(x) (((x) << INT_WLAN_VECTOR_LSB) & INT_WLAN_VECTOR_MASK)#define WINDOW_DATA_ADDRESS 0x00000474#define WINDOW_DATA_OFFSET 0x00000474#define WINDOW_DATA_DATA_MSB 7#define WINDOW_DATA_DATA_LSB 0#define WINDOW_DATA_DATA_MASK 0x000000ff#define WINDOW_DATA_DATA_GET(x) (((x) & WINDOW_DATA_DATA_MASK) >> WINDOW_DATA_DATA_LSB)#define WINDOW_DATA_DATA_SET(x) (((x) << WINDOW_DATA_DATA_LSB) & WINDOW_DATA_DATA_MASK)#define WINDOW_WRITE_ADDR_ADDRESS 0x00000478#define WINDOW_WRITE_ADDR_OFFSET 0x00000478#define WINDOW_WRITE_ADDR_ADDR_MSB 7#define WINDOW_WRITE_ADDR_ADDR_LSB 0#define WINDOW_WRITE_ADDR_ADDR_MASK 0x000000ff#define WINDOW_WRITE_ADDR_ADDR_GET(x) (((x) & WINDOW_WRITE_ADDR_ADDR_MASK) >> WINDOW_WRITE_ADDR_ADDR_LSB)#define WINDOW_WRITE_ADDR_ADDR_SET(x) (((x) << WINDOW_WRITE_ADDR_ADDR_LSB) & WINDOW_WRITE_ADDR_ADDR_MASK)#define WINDOW_READ_ADDR_ADDRESS 0x0000047c#define WINDOW_READ_ADDR_OFFSET 0x0000047c#define WINDOW_READ_ADDR_ADDR_MSB 7#define WINDOW_READ_ADDR_ADDR_LSB 0#define WINDOW_READ_ADDR_ADDR_MASK 0x000000ff#define WINDOW_READ_ADDR_ADDR_GET(x) (((x) & WINDOW_READ_ADDR_ADDR_MASK) >> WINDOW_READ_ADDR_ADDR_LSB)#define WINDOW_READ_ADDR_ADDR_SET(x) (((x) << WINDOW_READ_ADDR_ADDR_LSB) & WINDOW_READ_ADDR_ADDR_MASK)#define SPI_CONFIG_ADDRESS 0x00000480#define SPI_CONFIG_OFFSET 0x00000480#define SPI_CONFIG_SPI_RESET_MSB 4#define SPI_CONFIG_SPI_RESET_LSB 4#define SPI_CONFIG_SPI_RESET_MASK 0x00000010#define SPI_CONFIG_SPI_RESET_GET(x) (((x) & SPI_CONFIG_SPI_RESET_MASK) >> SPI_CONFIG_SPI_RESET_LSB)#define SPI_CONFIG_SPI_RESET_SET(x) (((x) << SPI_CONFIG_SPI_RESET_LSB) & SPI_CONFIG_SPI_RESET_MASK)#define SPI_CONFIG_INTERRUPT_ENABLE_MSB 3#define SPI_CONFIG_INTERRUPT_ENABLE_LSB 3#define SPI_CONFIG_INTERRUPT_ENABLE_MASK 0x00000008#define SPI_CONFIG_INTERRUPT_ENABLE_GET(x) (((x) & SPI_CONFIG_INTERRUPT_ENABLE_MASK) >> SPI_CONFIG_INTERRUPT_ENABLE_LSB)#define SPI_CONFIG_INTERRUPT_ENABLE_SET(x) (((x) << SPI_CONFIG_INTERRUPT_ENABLE_LSB) & SPI_CONFIG_INTERRUPT_ENABLE_MASK)#define SPI_CONFIG_TEST_MODE_MSB 2#define SPI_CONFIG_TEST_MODE_LSB 2#define SPI_CONFIG_TEST_MODE_MASK 0x00000004#define SPI_CONFIG_TEST_MODE_GET(x) (((x) & SPI_CONFIG_TEST_MODE_MASK) >> SPI_CONFIG_TEST_MODE_LSB)#define SPI_CONFIG_TEST_MODE_SET(x) (((x) << SPI_CONFIG_TEST_MODE_LSB) & SPI_CONFIG_TEST_MODE_MASK)#define SPI_CONFIG_DATA_SIZE_MSB 1#define SPI_CONFIG_DATA_SIZE_LSB 0#define SPI_CONFIG_DATA_SIZE_MASK 0x00000003#define SPI_CONFIG_DATA_SIZE_GET(x) (((x) & SPI_CONFIG_DATA_SIZE_MASK) >> SPI_CONFIG_DATA_SIZE_LSB)#define SPI_CONFIG_DATA_SIZE_SET(x) (((x) << SPI_CONFIG_DATA_SIZE_LSB) & SPI_CONFIG_DATA_SIZE_MASK)#define SPI_STATUS_ADDRESS 0x00000481#define SPI_STATUS_OFFSET 0x00000481#define SPI_STATUS_ADDR_ERR_MSB 3#define SPI_STATUS_ADDR_ERR_LSB 3#define SPI_STATUS_ADDR_ERR_MASK 0x00000008#define SPI_STATUS_ADDR_ERR_GET(x) (((x) & SPI_STATUS_ADDR_ERR_MASK) >> SPI_STATUS_ADDR_ERR_LSB)#define SPI_STATUS_ADDR_ERR_SET(x) (((x) << SPI_STATUS_ADDR_ERR_LSB) & SPI_STATUS_ADDR_ERR_MASK)#define SPI_STATUS_RD_ERR_MSB 2#define SPI_STATUS_RD_ERR_LSB 2#define SPI_STATUS_RD_ERR_MASK 0x00000004#define SPI_STATUS_RD_ERR_GET(x) (((x) & SPI_STATUS_RD_ERR_MASK) >> SPI_STATUS_RD_ERR_LSB)#define SPI_STATUS_RD_ERR_SET(x) (((x) << SPI_STATUS_RD_ERR_LSB) & SPI_STATUS_RD_ERR_MASK)#define SPI_STATUS_WR_ERR_MSB 1#define SPI_STATUS_WR_ERR_LSB 1#define SPI_STATUS_WR_ERR_MASK 0x00000002#define SPI_STATUS_WR_ERR_GET(x) (((x) & SPI_STATUS_WR_ERR_MASK) >> SPI_STATUS_WR_ERR_LSB)#define SPI_STATUS_WR_ERR_SET(x) (((x) << SPI_STATUS_WR_ERR_LSB) & SPI_STATUS_WR_ERR_MASK)#define SPI_STATUS_READY_MSB 0#define SPI_STATUS_READY_LSB 0#define SPI_STATUS_READY_MASK 0x00000001#define SPI_STATUS_READY_GET(x) (((x) & SPI_STATUS_READY_MASK) >> SPI_STATUS_READY_LSB)#define SPI_STATUS_READY_SET(x) (((x) << SPI_STATUS_READY_LSB) & SPI_STATUS_READY_MASK)#define CIS_WINDOW_ADDRESS 0x00000600#define CIS_WINDOW_OFFSET 0x00000600#define CIS_WINDOW_DATA_MSB 7#define CIS_WINDOW_DATA_LSB 0#define CIS_WINDOW_DATA_MASK 0x000000ff#define CIS_WINDOW_DATA_GET(x) (((x) & CIS_WINDOW_DATA_MASK) >> CIS_WINDOW_DATA_LSB)#define CIS_WINDOW_DATA_SET(x) (((x) << CIS_WINDOW_DATA_LSB) & CIS_WINDOW_DATA_MASK)#ifndef __ASSEMBLER__typedef struct mbox_host_reg_reg_s { unsigned char pad0[1024]; /* pad to 0x400 */ volatile unsigned char host_int_status; volatile unsigned char cpu_int_status; volatile unsigned char error_int_status; volatile unsigned char counter_int_status; volatile unsigned char mbox_frame; volatile unsigned char rx_lookahead_valid; unsigned char pad1[2]; /* pad to 0x408 */ volatile unsigned char rx_lookahead0[4]; volatile unsigned char rx_lookahead1[4]; volatile unsigned char rx_lookahead2[4]; volatile unsigned char rx_lookahead3[4]; volatile unsigned char int_status_enable; volatile unsigned char cpu_int_status_enable; volatile unsigned char error_status_enable; volatile unsigned char counter_int_status_enable; unsigned char pad2[4]; /* pad to 0x420 */ volatile unsigned char count[8]; unsigned char pad3[24]; /* pad to 0x440 */ volatile unsigned char count_dec[32]; volatile unsigned char scratch[8]; volatile unsigned char fifo_timeout; volatile unsigned char fifo_timeout_enable; volatile unsigned char disable_sleep; unsigned char pad4[3]; /* pad to 0x46e */ volatile unsigned char local_bus_endian; unsigned char pad5[1]; /* pad to 0x470 */ volatile unsigned char local_bus; unsigned char pad6[1]; /* pad to 0x472 */ volatile unsigned char int_wlan; unsigned char pad7[1]; /* pad to 0x474 */ volatile unsigned char window_data[4]; volatile unsigned char window_write_addr[4]; volatile unsigned char window_read_addr[4]; volatile unsigned char spi_config; volatile unsigned char spi_status; unsigned char pad8[382]; /* pad to 0x600 */ volatile unsigned char cis_window[512];} mbox_host_reg_reg_t;#endif /* __ASSEMBLER__ */#endif /* _MBOX_HOST_REG_H_ */⌨️ 快捷键说明
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