mbox_host_reg.h

linux下的SDIO 驱动

/*
 * Copyright 2006 Atheros Communications, Inc.
 *
 *  Wireless Network driver for Atheros AR6001
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License version 2 as
 *  published by the Free Software Foundation;
 *
 *  Software distributed under the License is distributed on an "AS
 *  IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
 *  implied. See the License for the specific language governing
 *  rights and limitations under the License.
 *
 *
 */

#ifndef _MBOX_HOST_REG_REG_H_
#define _MBOX_HOST_REG_REG_H_

#define HOST_INT_STATUS_ADDRESS                  0x00000400
#define HOST_INT_STATUS_OFFSET                   0x00000400
#define HOST_INT_STATUS_ERROR_MSB                7
#define HOST_INT_STATUS_ERROR_LSB                7
#define HOST_INT_STATUS_ERROR_MASK               0x00000080
#define HOST_INT_STATUS_ERROR_GET(x)             (((x) & HOST_INT_STATUS_ERROR_MASK) >> HOST_INT_STATUS_ERROR_LSB)
#define HOST_INT_STATUS_ERROR_SET(x)             (((x) << HOST_INT_STATUS_ERROR_LSB) & HOST_INT_STATUS_ERROR_MASK)
#define HOST_INT_STATUS_CPU_MSB                  6
#define HOST_INT_STATUS_CPU_LSB                  6
#define HOST_INT_STATUS_CPU_MASK                 0x00000040
#define HOST_INT_STATUS_CPU_GET(x)               (((x) & HOST_INT_STATUS_CPU_MASK) >> HOST_INT_STATUS_CPU_LSB)
#define HOST_INT_STATUS_CPU_SET(x)               (((x) << HOST_INT_STATUS_CPU_LSB) & HOST_INT_STATUS_CPU_MASK)
#define HOST_INT_STATUS_DRAGON_INT_MSB           5
#define HOST_INT_STATUS_DRAGON_INT_LSB           5
#define HOST_INT_STATUS_DRAGON_INT_MASK          0x00000020
#define HOST_INT_STATUS_DRAGON_INT_GET(x)        (((x) & HOST_INT_STATUS_DRAGON_INT_MASK) >> HOST_INT_STATUS_DRAGON_INT_LSB)
#define HOST_INT_STATUS_DRAGON_INT_SET(x)        (((x) << HOST_INT_STATUS_DRAGON_INT_LSB) & HOST_INT_STATUS_DRAGON_INT_MASK)
#define HOST_INT_STATUS_COUNTER_MSB              4
#define HOST_INT_STATUS_COUNTER_LSB              4
#define HOST_INT_STATUS_COUNTER_MASK             0x00000010
#define HOST_INT_STATUS_COUNTER_GET(x)           (((x) & HOST_INT_STATUS_COUNTER_MASK) >> HOST_INT_STATUS_COUNTER_LSB)
#define HOST_INT_STATUS_COUNTER_SET(x)           (((x) << HOST_INT_STATUS_COUNTER_LSB) & HOST_INT_STATUS_COUNTER_MASK)
#define HOST_INT_STATUS_MBOX_DATA_MSB            3
#define HOST_INT_STATUS_MBOX_DATA_LSB            0
#define HOST_INT_STATUS_MBOX_DATA_MASK           0x0000000f
#define HOST_INT_STATUS_MBOX_DATA_GET(x)         (((x) & HOST_INT_STATUS_MBOX_DATA_MASK) >> HOST_INT_STATUS_MBOX_DATA_LSB)
#define HOST_INT_STATUS_MBOX_DATA_SET(x)         (((x) << HOST_INT_STATUS_MBOX_DATA_LSB) & HOST_INT_STATUS_MBOX_DATA_MASK)

#define CPU_INT_STATUS_ADDRESS                   0x00000401
#define CPU_INT_STATUS_OFFSET                    0x00000401
#define CPU_INT_STATUS_BIT_MSB                   7
#define CPU_INT_STATUS_BIT_LSB                   0
#define CPU_INT_STATUS_BIT_MASK                  0x000000ff
#define CPU_INT_STATUS_BIT_GET(x)                (((x) & CPU_INT_STATUS_BIT_MASK) >> CPU_INT_STATUS_BIT_LSB)
#define CPU_INT_STATUS_BIT_SET(x)                (((x) << CPU_INT_STATUS_BIT_LSB) & CPU_INT_STATUS_BIT_MASK)

#define ERROR_INT_STATUS_ADDRESS                 0x00000402
#define ERROR_INT_STATUS_OFFSET                  0x00000402
#define ERROR_INT_STATUS_SPI_MSB                 3
#define ERROR_INT_STATUS_SPI_LSB                 3
#define ERROR_INT_STATUS_SPI_MASK                0x00000008
#define ERROR_INT_STATUS_SPI_GET(x)              (((x) & ERROR_INT_STATUS_SPI_MASK) >> ERROR_INT_STATUS_SPI_LSB)
#define ERROR_INT_STATUS_SPI_SET(x)              (((x) << ERROR_INT_STATUS_SPI_LSB) & ERROR_INT_STATUS_SPI_MASK)
#define ERROR_INT_STATUS_WAKEUP_MSB              2
#define ERROR_INT_STATUS_WAKEUP_LSB              2
#define ERROR_INT_STATUS_WAKEUP_MASK             0x00000004
#define ERROR_INT_STATUS_WAKEUP_GET(x)           (((x) & ERROR_INT_STATUS_WAKEUP_MASK) >> ERROR_INT_STATUS_WAKEUP_LSB)
#define ERROR_INT_STATUS_WAKEUP_SET(x)           (((x) << ERROR_INT_STATUS_WAKEUP_LSB) & ERROR_INT_STATUS_WAKEUP_MASK)
#define ERROR_INT_STATUS_RX_UNDERFLOW_MSB        1
#define ERROR_INT_STATUS_RX_UNDERFLOW_LSB        1
#define ERROR_INT_STATUS_RX_UNDERFLOW_MASK       0x00000002
#define ERROR_INT_STATUS_RX_UNDERFLOW_GET(x)     (((x) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK) >> ERROR_INT_STATUS_RX_UNDERFLOW_LSB)
#define ERROR_INT_STATUS_RX_UNDERFLOW_SET(x)     (((x) << ERROR_INT_STATUS_RX_UNDERFLOW_LSB) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK)
#define ERROR_INT_STATUS_TX_OVERFLOW_MSB         0
#define ERROR_INT_STATUS_TX_OVERFLOW_LSB         0
#define ERROR_INT_STATUS_TX_OVERFLOW_MASK        0x00000001
#define ERROR_INT_STATUS_TX_OVERFLOW_GET(x)      (((x) & ERROR_INT_STATUS_TX_OVERFLOW_MASK) >> ERROR_INT_STATUS_TX_OVERFLOW_LSB)
#define ERROR_INT_STATUS_TX_OVERFLOW_SET(x)      (((x) << ERROR_INT_STATUS_TX_OVERFLOW_LSB) & ERROR_INT_STATUS_TX_OVERFLOW_MASK)

#define COUNTER_INT_STATUS_ADDRESS               0x00000403
#define COUNTER_INT_STATUS_OFFSET                0x00000403
#define COUNTER_INT_STATUS_COUNTER_MSB           7
#define COUNTER_INT_STATUS_COUNTER_LSB           0
#define COUNTER_INT_STATUS_COUNTER_MASK          0x000000ff
#define COUNTER_INT_STATUS_COUNTER_GET(x)        (((x) & COUNTER_INT_STATUS_COUNTER_MASK) >> COUNTER_INT_STATUS_COUNTER_LSB)
#define COUNTER_INT_STATUS_COUNTER_SET(x)        (((x) << COUNTER_INT_STATUS_COUNTER_LSB) & COUNTER_INT_STATUS_COUNTER_MASK)

#define MBOX_FRAME_ADDRESS                       0x00000404
#define MBOX_FRAME_OFFSET                        0x00000404
#define MBOX_FRAME_RX_EOM_MSB                    7
#define MBOX_FRAME_RX_EOM_LSB                    4
#define MBOX_FRAME_RX_EOM_MASK                   0x000000f0
#define MBOX_FRAME_RX_EOM_GET(x)                 (((x) & MBOX_FRAME_RX_EOM_MASK) >> MBOX_FRAME_RX_EOM_LSB)
#define MBOX_FRAME_RX_EOM_SET(x)                 (((x) << MBOX_FRAME_RX_EOM_LSB) & MBOX_FRAME_RX_EOM_MASK)
#define MBOX_FRAME_RX_SOM_MSB                    3
#define MBOX_FRAME_RX_SOM_LSB                    0
#define MBOX_FRAME_RX_SOM_MASK                   0x0000000f
#define MBOX_FRAME_RX_SOM_GET(x)                 (((x) & MBOX_FRAME_RX_SOM_MASK) >> MBOX_FRAME_RX_SOM_LSB)
#define MBOX_FRAME_RX_SOM_SET(x)                 (((x) << MBOX_FRAME_RX_SOM_LSB) & MBOX_FRAME_RX_SOM_MASK)

#define RX_LOOKAHEAD_VALID_ADDRESS               0x00000405
#define RX_LOOKAHEAD_VALID_OFFSET                0x00000405
#define RX_LOOKAHEAD_VALID_MBOX_MSB              3
#define RX_LOOKAHEAD_VALID_MBOX_LSB              0
#define RX_LOOKAHEAD_VALID_MBOX_MASK             0x0000000f
#define RX_LOOKAHEAD_VALID_MBOX_GET(x)           (((x) & RX_LOOKAHEAD_VALID_MBOX_MASK) >> RX_LOOKAHEAD_VALID_MBOX_LSB)
#define RX_LOOKAHEAD_VALID_MBOX_SET(x)           (((x) << RX_LOOKAHEAD_VALID_MBOX_LSB) & RX_LOOKAHEAD_VALID_MBOX_MASK)

#define RX_LOOKAHEAD0_ADDRESS                    0x00000408
#define RX_LOOKAHEAD0_OFFSET                     0x00000408
#define RX_LOOKAHEAD0_DATA_MSB                   7
#define RX_LOOKAHEAD0_DATA_LSB                   0
#define RX_LOOKAHEAD0_DATA_MASK                  0x000000ff
#define RX_LOOKAHEAD0_DATA_GET(x)                (((x) & RX_LOOKAHEAD0_DATA_MASK) >> RX_LOOKAHEAD0_DATA_LSB)
#define RX_LOOKAHEAD0_DATA_SET(x)                (((x) << RX_LOOKAHEAD0_DATA_LSB) & RX_LOOKAHEAD0_DATA_MASK)

#define RX_LOOKAHEAD1_ADDRESS                    0x0000040c
#define RX_LOOKAHEAD1_OFFSET                     0x0000040c
#define RX_LOOKAHEAD1_DATA_MSB                   7
#define RX_LOOKAHEAD1_DATA_LSB                   0
#define RX_LOOKAHEAD1_DATA_MASK                  0x000000ff
#define RX_LOOKAHEAD1_DATA_GET(x)                (((x) & RX_LOOKAHEAD1_DATA_MASK) >> RX_LOOKAHEAD1_DATA_LSB)
#define RX_LOOKAHEAD1_DATA_SET(x)                (((x) << RX_LOOKAHEAD1_DATA_LSB) & RX_LOOKAHEAD1_DATA_MASK)

#define RX_LOOKAHEAD2_ADDRESS                    0x00000410
#define RX_LOOKAHEAD2_OFFSET                     0x00000410
#define RX_LOOKAHEAD2_DATA_MSB                   7
#define RX_LOOKAHEAD2_DATA_LSB                   0
#define RX_LOOKAHEAD2_DATA_MASK                  0x000000ff
#define RX_LOOKAHEAD2_DATA_GET(x)                (((x) & RX_LOOKAHEAD2_DATA_MASK) >> RX_LOOKAHEAD2_DATA_LSB)
#define RX_LOOKAHEAD2_DATA_SET(x)                (((x) << RX_LOOKAHEAD2_DATA_LSB) & RX_LOOKAHEAD2_DATA_MASK)

#define RX_LOOKAHEAD3_ADDRESS                    0x00000414
#define RX_LOOKAHEAD3_OFFSET                     0x00000414
#define RX_LOOKAHEAD3_DATA_MSB                   7
#define RX_LOOKAHEAD3_DATA_LSB                   0
#define RX_LOOKAHEAD3_DATA_MASK                  0x000000ff
#define RX_LOOKAHEAD3_DATA_GET(x)                (((x) & RX_LOOKAHEAD3_DATA_MASK) >> RX_LOOKAHEAD3_DATA_LSB)
#define RX_LOOKAHEAD3_DATA_SET(x)                (((x) << RX_LOOKAHEAD3_DATA_LSB) & RX_LOOKAHEAD3_DATA_MASK)

#define INT_STATUS_ENABLE_ADDRESS                0x00000418
#define INT_STATUS_ENABLE_OFFSET                 0x00000418
#define INT_STATUS_ENABLE_ERROR_MSB              7
#define INT_STATUS_ENABLE_ERROR_LSB              7
#define INT_STATUS_ENABLE_ERROR_MASK             0x00000080
#define INT_STATUS_ENABLE_ERROR_GET(x)           (((x) & INT_STATUS_ENABLE_ERROR_MASK) >> INT_STATUS_ENABLE_ERROR_LSB)
#define INT_STATUS_ENABLE_ERROR_SET(x)           (((x) << INT_STATUS_ENABLE_ERROR_LSB) & INT_STATUS_ENABLE_ERROR_MASK)
#define INT_STATUS_ENABLE_CPU_MSB                6
#define INT_STATUS_ENABLE_CPU_LSB                6
#define INT_STATUS_ENABLE_CPU_MASK               0x00000040
#define INT_STATUS_ENABLE_CPU_GET(x)             (((x) & INT_STATUS_ENABLE_CPU_MASK) >> INT_STATUS_ENABLE_CPU_LSB)
#define INT_STATUS_ENABLE_CPU_SET(x)             (((x) << INT_STATUS_ENABLE_CPU_LSB) & INT_STATUS_ENABLE_CPU_MASK)
#define INT_STATUS_ENABLE_DRAGON_INT_MSB         5
#define INT_STATUS_ENABLE_DRAGON_INT_LSB         5
#define INT_STATUS_ENABLE_DRAGON_INT_MASK        0x00000020
#define INT_STATUS_ENABLE_DRAGON_INT_GET(x)      (((x) & INT_STATUS_ENABLE_DRAGON_INT_MASK) >> INT_STATUS_ENABLE_DRAGON_INT_LSB)
#define INT_STATUS_ENABLE_DRAGON_INT_SET(x)      (((x) << INT_STATUS_ENABLE_DRAGON_INT_LSB) & INT_STATUS_ENABLE_DRAGON_INT_MASK)
#define INT_STATUS_ENABLE_COUNTER_MSB            4
#define INT_STATUS_ENABLE_COUNTER_LSB            4
#define INT_STATUS_ENABLE_COUNTER_MASK           0x00000010
#define INT_STATUS_ENABLE_COUNTER_GET(x)         (((x) & INT_STATUS_ENABLE_COUNTER_MASK) >> INT_STATUS_ENABLE_COUNTER_LSB)
#define INT_STATUS_ENABLE_COUNTER_SET(x)         (((x) << INT_STATUS_ENABLE_COUNTER_LSB) & INT_STATUS_ENABLE_COUNTER_MASK)
#define INT_STATUS_ENABLE_MBOX_DATA_MSB          3
#define INT_STATUS_ENABLE_MBOX_DATA_LSB          0
#define INT_STATUS_ENABLE_MBOX_DATA_MASK         0x0000000f
#define INT_STATUS_ENABLE_MBOX_DATA_GET(x)       (((x) & INT_STATUS_ENABLE_MBOX_DATA_MASK) >> INT_STATUS_ENABLE_MBOX_DATA_LSB)
#define INT_STATUS_ENABLE_MBOX_DATA_SET(x)       (((x) << INT_STATUS_ENABLE_MBOX_DATA_LSB) & INT_STATUS_ENABLE_MBOX_DATA_MASK)

#define CPU_INT_STATUS_ENABLE_ADDRESS            0x00000419
#define CPU_INT_STATUS_ENABLE_OFFSET             0x00000419
#define CPU_INT_STATUS_ENABLE_BIT_MSB            7
#define CPU_INT_STATUS_ENABLE_BIT_LSB            0
#define CPU_INT_STATUS_ENABLE_BIT_MASK           0x000000ff
#define CPU_INT_STATUS_ENABLE_BIT_GET(x)         (((x) & CPU_INT_STATUS_ENABLE_BIT_MASK) >> CPU_INT_STATUS_ENABLE_BIT_LSB)
#define CPU_INT_STATUS_ENABLE_BIT_SET(x)         (((x) << CPU_INT_STATUS_ENABLE_BIT_LSB) & CPU_INT_STATUS_ENABLE_BIT_MASK)

#define ERROR_STATUS_ENABLE_ADDRESS              0x0000041a
#define ERROR_STATUS_ENABLE_OFFSET               0x0000041a
#define ERROR_STATUS_ENABLE_WAKEUP_MSB           2
#define ERROR_STATUS_ENABLE_WAKEUP_LSB           2
#define ERROR_STATUS_ENABLE_WAKEUP_MASK          0x00000004
#define ERROR_STATUS_ENABLE_WAKEUP_GET(x)        (((x) & ERROR_STATUS_ENABLE_WAKEUP_MASK) >> ERROR_STATUS_ENABLE_WAKEUP_LSB)
#define ERROR_STATUS_ENABLE_WAKEUP_SET(x)        (((x) << ERROR_STATUS_ENABLE_WAKEUP_LSB) & ERROR_STATUS_ENABLE_WAKEUP_MASK)
#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MSB     1
#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB     1
#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK    0x00000002
#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_GET(x)  (((x) & ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK) >> ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB)
#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_SET(x)  (((x) << ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) & ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK)
#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MSB      0
#define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB      0
#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK     0x00000001
#define ERROR_STATUS_ENABLE_TX_OVERFLOW_GET(x)   (((x) & ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK) >> ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB)
#define ERROR_STATUS_ENABLE_TX_OVERFLOW_SET(x)   (((x) << ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) & ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK)

#define COUNTER_INT_STATUS_ENABLE_ADDRESS        0x0000041b
#define COUNTER_INT_STATUS_ENABLE_OFFSET         0x0000041b
#define COUNTER_INT_STATUS_ENABLE_BIT_MSB        7
#define COUNTER_INT_STATUS_ENABLE_BIT_LSB        0
#define COUNTER_INT_STATUS_ENABLE_BIT_MASK       0x000000ff
#define COUNTER_INT_STATUS_ENABLE_BIT_GET(x)     (((x) & COUNTER_INT_STATUS_ENABLE_BIT_MASK) >> COUNTER_INT_STATUS_ENABLE_BIT_LSB)
#define COUNTER_INT_STATUS_ENABLE_BIT_SET(x)     (((x) << COUNTER_INT_STATUS_ENABLE_BIT_LSB) & COUNTER_INT_STATUS_ENABLE_BIT_MASK)

#define COUNT_ADDRESS                            0x00000420
#define COUNT_OFFSET                             0x00000420
#define COUNT_VALUE_MSB                          7
#define COUNT_VALUE_LSB                          0
#define COUNT_VALUE_MASK                         0x000000ff
#define COUNT_VALUE_GET(x)                       (((x) & COUNT_VALUE_MASK) >> COUNT_VALUE_LSB)
#define COUNT_VALUE_SET(x)                       (((x) << COUNT_VALUE_LSB) & COUNT_VALUE_MASK)