e_7_seg.vhd

来自「书籍以及一些资料 还有些源程序 这是vhde相当珍贵的教材」· VHDL 代码 · 共 25 行

library ieee;
use ieee.std_logic_1164.all;

entity E_7_seg is
PORT ( C : IN STD_logic_vector(2 DOWNTO 0);
       Display : OUT STD_logic_vector(0 TO 6));
end E_7_seg;

ARCHITECTURE Behavior OF E_7_seg IS
BEGIN

process(c)
begin

case c is
when "000" =>display<="1001000";
when "001" =>display<="0110000";
when "010" =>display<="1110001";
when "011" =>display<="0000001";
when others =>display<="1111111";
end case;

end process;

END Behavior;