📄 shfrt.tan.qmsg
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{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "CLK register register REG8\[6\] REG8\[5\] 422.12 MHz Internal " "Info: Clock \"CLK\" Internal fmax is restricted to 422.12 MHz between source register \"REG8\[6\]\" and destination register \"REG8\[5\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.369 ns " "Info: fmax restricted to clock pin edge rate 2.369 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.931 ns + Longest register register " "Info: + Longest register to register delay is 0.931 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns REG8\[6\] 1 REG LC_X12_Y30_N7 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y30_N7; Fanout = 1; REG Node = 'REG8\[6\]'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shfrt" "UNKNOWN" "V1" "D:/altera/shfrt/db/shfrt.quartus_db" { Floorplan "D:/altera/shfrt/" "" "" { REG8[6] } "NODE_NAME" } "" } } { "../quartus51/shfrt.vhd" "" { Text "D:/altera/quartus51/shfrt.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.392 ns) + CELL(0.539 ns) 0.931 ns REG8\[5\] 2 REG LC_X12_Y30_N5 1 " "Info: 2: + IC(0.392 ns) + CELL(0.539 ns) = 0.931 ns; Loc. = LC_X12_Y30_N5; Fanout = 1; REG Node = 'REG8\[5\]'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shfrt" "UNKNOWN" "V1" "D:/altera/shfrt/db/shfrt.quartus_db" { Floorplan "D:/altera/shfrt/" "" "0.931 ns" { REG8[6] REG8[5] } "NODE_NAME" } "" } } { "../quartus51/shfrt.vhd" "" { Text "D:/altera/quartus51/shfrt.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.539 ns ( 57.89 % ) " "Info: Total cell delay = 0.539 ns ( 57.89 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.392 ns ( 42.11 % ) " "Info: Total interconnect delay = 0.392 ns ( 42.11 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shfrt" "UNKNOWN" "V1" "D:/altera/shfrt/db/shfrt.quartus_db" { Floorplan "D:/altera/shfrt/" "" "0.931 ns" { REG8[6] REG8[5] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "0.931 ns" { REG8[6] REG8[5] } { 0.000ns 0.392ns } { 0.000ns 0.539ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.853 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 2.853 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns CLK 1 CLK PIN_L2 8 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 8; CLK Node = 'CLK'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shfrt" "UNKNOWN" "V1" "D:/altera/shfrt/db/shfrt.quartus_db" { Floorplan "D:/altera/shfrt/" "" "" { CLK } "NODE_NAME" } "" } } { "../quartus51/shfrt.vhd" "" { Text "D:/altera/quartus51/shfrt.vhd" 4 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.586 ns) + CELL(0.542 ns) 2.853 ns REG8\[5\] 2 REG LC_X12_Y30_N5 1 " "Info: 2: + IC(1.586 ns) + CELL(0.542 ns) = 2.853 ns; Loc. = LC_X12_Y30_N5; Fanout = 1; REG Node = 'REG8\[5\]'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shfrt" "UNKNOWN" "V1" "D:/altera/shfrt/db/shfrt.quartus_db" { Floorplan "D:/altera/shfrt/" "" "2.128 ns" { CLK REG8[5] } "NODE_NAME" } "" } } { "../quartus51/shfrt.vhd" "" { Text "D:/altera/quartus51/shfrt.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns ( 44.41 % ) " "Info: Total cell delay = 1.267 ns ( 44.41 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.586 ns ( 55.59 % ) " "Info: Total interconnect delay = 1.586 ns ( 55.59 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shfrt" "UNKNOWN" "V1" "D:/altera/shfrt/db/shfrt.quartus_db" { Floorplan "D:/altera/shfrt/" "" "2.853 ns" { CLK REG8[5] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.853 ns" { CLK CLK~out0 REG8[5] } { 0.000ns 0.000ns 1.586ns } { 0.000ns 0.725ns 0.542ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.853 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 2.853 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns CLK 1 CLK PIN_L2 8 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 8; CLK Node = 'CLK'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shfrt" "UNKNOWN" "V1" "D:/altera/shfrt/db/shfrt.quartus_db" { Floorplan "D:/altera/shfrt/" "" "" { CLK } "NODE_NAME" } "" } } { "../quartus51/shfrt.vhd" "" { Text "D:/altera/quartus51/shfrt.vhd" 4 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.586 ns) + CELL(0.542 ns) 2.853 ns REG8\[6\] 2 REG LC_X12_Y30_N7 1 " "Info: 2: + IC(1.586 ns) + CELL(0.542 ns) = 2.853 ns; Loc. = LC_X12_Y30_N7; Fanout = 1; REG Node = 'REG8\[6\]'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shfrt" "UNKNOWN" "V1" "D:/altera/shfrt/db/shfrt.quartus_db" { Floorplan "D:/altera/shfrt/" "" "2.128 ns" { CLK REG8[6] } "NODE_NAME" } "" } } { "../quartus51/shfrt.vhd" "" { Text "D:/altera/quartus51/shfrt.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns ( 44.41 % ) " "Info: Total cell delay = 1.267 ns ( 44.41 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.586 ns ( 55.59 % ) " "Info: Total interconnect delay = 1.586 ns ( 55.59 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shfrt" "UNKNOWN" "V1" "D:/altera/shfrt/db/shfrt.quartus_db" { Floorplan "D:/altera/shfrt/" "" "2.853 ns" { CLK REG8[6] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.853 ns" { CLK CLK~out0 REG8[6] } { 0.000ns 0.000ns 1.586ns } { 0.000ns 0.725ns 0.542ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shfrt" "UNKNOWN" "V1" "D:/altera/shfrt/db/shfrt.quartus_db" { Floorplan "D:/altera/shfrt/" "" "2.853 ns" { CLK REG8[5] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.853 ns" { CLK CLK~out0 REG8[5] } { 0.000ns 0.000ns 1.586ns } { 0.000ns 0.725ns 0.542ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shfrt" "UNKNOWN" "V1" "D:/altera/shfrt/db/shfrt.quartus_db" { Floorplan "D:/altera/shfrt/" "" "2.853 ns" { CLK REG8[6] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.853 ns" { CLK CLK~out0 REG8[6] } { 0.000ns 0.000ns 1.586ns } { 0.000ns 0.725ns 0.542ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" { } { { "../quartus51/shfrt.vhd" "" { Text "D:/altera/quartus51/shfrt.vhd" 13 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" { } { { "../quartus51/shfrt.vhd" "" { Text "D:/altera/quartus51/shfrt.vhd" 13 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shfrt" "UNKNOWN" "V1" "D:/altera/shfrt/db/shfrt.quartus_db" { Floorplan "D:/altera/shfrt/" "" "0.931 ns" { REG8[6] REG8[5] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "0.931 ns" { REG8[6] REG8[5] } { 0.000ns 0.392ns } { 0.000ns 0.539ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shfrt" "UNKNOWN" "V1" "D:/altera/shfrt/db/shfrt.quartus_db" { Floorplan "D:/altera/shfrt/" "" "2.853 ns" { CLK REG8[5] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.853 ns" { CLK CLK~out0 REG8[5] } { 0.000ns 0.000ns 1.586ns } { 0.000ns 0.725ns 0.542ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shfrt" "UNKNOWN" "V1" "D:/altera/shfrt/db/shfrt.quartus_db" { Floorplan "D:/altera/shfrt/" "" "2.853 ns" { CLK REG8[6] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.853 ns" { CLK CLK~out0 REG8[6] } { 0.000ns 0.000ns 1.586ns } { 0.000ns 0.725ns 0.542ns } } } } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shfrt" "UNKNOWN" "V1" "D:/altera/shfrt/db/shfrt.quartus_db" { Floorplan "D:/altera/shfrt/" "" "" { REG8[5] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { REG8[5] } { } { } } } { "../quartus51/shfrt.vhd" "" { Text "D:/altera/quartus51/shfrt.vhd" 13 -1 0 } } } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "REG8\[3\] DIN\[3\] CLK 2.674 ns register " "Info: tsu for register \"REG8\[3\]\" (data pin = \"DIN\[3\]\", clock pin = \"CLK\") is 2.674 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.517 ns + Longest pin register " "Info: + Longest pin to register delay is 5.517 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.234 ns) 1.234 ns DIN\[3\] 1 PIN PIN_E20 1 " "Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_E20; Fanout = 1; PIN Node = 'DIN\[3\]'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shfrt" "UNKNOWN" "V1" "D:/altera/shfrt/db/shfrt.quartus_db" { Floorplan "D:/altera/shfrt/" "" "" { DIN[3] } "NODE_NAME" } "" } } { "../quartus51/shfrt.vhd" "" { Text "D:/altera/quartus51/shfrt.vhd" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.744 ns) + CELL(0.539 ns) 5.517 ns REG8\[3\] 2 REG LC_X12_Y30_N2 1 " "Info: 2: + IC(3.744 ns) + CELL(0.539 ns) = 5.517 ns; Loc. = LC_X12_Y30_N2; Fanout = 1; REG Node = 'REG8\[3\]'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shfrt" "UNKNOWN" "V1" "D:/altera/shfrt/db/shfrt.quartus_db" { Floorplan "D:/altera/shfrt/" "" "4.283 ns" { DIN[3] REG8[3] } "NODE_NAME" } "" } } { "../quartus51/shfrt.vhd" "" { Text "D:/altera/quartus51/shfrt.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.773 ns ( 32.14 % ) " "Info: Total cell delay = 1.773 ns ( 32.14 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.744 ns ( 67.86 % ) " "Info: Total interconnect delay = 3.744 ns ( 67.86 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shfrt" "UNKNOWN" "V1" "D:/altera/shfrt/db/shfrt.quartus_db" { Floorplan "D:/altera/shfrt/" "" "5.517 ns" { DIN[3] REG8[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.517 ns" { DIN[3] DIN[3]~out0 REG8[3] } { 0.000ns 0.000ns 3.744ns } { 0.000ns 1.234ns 0.539ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" { } { { "../quartus51/shfrt.vhd" "" { Text "D:/altera/quartus51/shfrt.vhd" 13 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.853 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 2.853 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns CLK 1 CLK PIN_L2 8 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 8; CLK Node = 'CLK'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shfrt" "UNKNOWN" "V1" "D:/altera/shfrt/db/shfrt.quartus_db" { Floorplan "D:/altera/shfrt/" "" "" { CLK } "NODE_NAME" } "" } } { "../quartus51/shfrt.vhd" "" { Text "D:/altera/quartus51/shfrt.vhd" 4 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.586 ns) + CELL(0.542 ns) 2.853 ns REG8\[3\] 2 REG LC_X12_Y30_N2 1 " "Info: 2: + IC(1.586 ns) + CELL(0.542 ns) = 2.853 ns; Loc. = LC_X12_Y30_N2; Fanout = 1; REG Node = 'REG8\[3\]'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shfrt" "UNKNOWN" "V1" "D:/altera/shfrt/db/shfrt.quartus_db" { Floorplan "D:/altera/shfrt/" "" "2.128 ns" { CLK REG8[3] } "NODE_NAME" } "" } } { "../quartus51/shfrt.vhd" "" { Text "D:/altera/quartus51/shfrt.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns ( 44.41 % ) " "Info: Total cell delay = 1.267 ns ( 44.41 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.586 ns ( 55.59 % ) " "Info: Total interconnect delay = 1.586 ns ( 55.59 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shfrt" "UNKNOWN" "V1" "D:/altera/shfrt/db/shfrt.quartus_db" { Floorplan "D:/altera/shfrt/" "" "2.853 ns" { CLK REG8[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.853 ns" { CLK CLK~out0 REG8[3] } { 0.000ns 0.000ns 1.586ns } { 0.000ns 0.725ns 0.542ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shfrt" "UNKNOWN" "V1" "D:/altera/shfrt/db/shfrt.quartus_db" { Floorplan "D:/altera/shfrt/" "" "5.517 ns" { DIN[3] REG8[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.517 ns" { DIN[3] DIN[3]~out0 REG8[3] } { 0.000ns 0.000ns 3.744ns } { 0.000ns 1.234ns 0.539ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shfrt" "UNKNOWN" "V1" "D:/altera/shfrt/db/shfrt.quartus_db" { Floorplan "D:/altera/shfrt/" "" "2.853 ns" { CLK REG8[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.853 ns" { CLK CLK~out0 REG8[3] } { 0.000ns 0.000ns 1.586ns } { 0.000ns 0.725ns 0.542ns } } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK QB REG8\[0\] 8.225 ns register " "Info: tco from clock \"CLK\" to destination pin \"QB\" through register \"REG8\[0\]\" is 8.225 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.853 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 2.853 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns CLK 1 CLK PIN_L2 8 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 8; CLK Node = 'CLK'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shfrt" "UNKNOWN" "V1" "D:/altera/shfrt/db/shfrt.quartus_db" { Floorplan "D:/altera/shfrt/" "" "" { CLK } "NODE_NAME" } "" } } { "../quartus51/shfrt.vhd" "" { Text "D:/altera/quartus51/shfrt.vhd" 4 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.586 ns) + CELL(0.542 ns) 2.853 ns REG8\[0\] 2 REG LC_X12_Y30_N3 1 " "Info: 2: + IC(1.586 ns) + CELL(0.542 ns) = 2.853 ns; Loc. = LC_X12_Y30_N3; Fanout = 1; REG Node = 'REG8\[0\]'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shfrt" "UNKNOWN" "V1" "D:/altera/shfrt/db/shfrt.quartus_db" { Floorplan "D:/altera/shfrt/" "" "2.128 ns" { CLK REG8[0] } "NODE_NAME" } "" } } { "../quartus51/shfrt.vhd" "" { Text "D:/altera/quartus51/shfrt.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns ( 44.41 % ) " "Info: Total cell delay = 1.267 ns ( 44.41 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.586 ns ( 55.59 % ) " "Info: Total interconnect delay = 1.586 ns ( 55.59 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shfrt" "UNKNOWN" "V1" "D:/altera/shfrt/db/shfrt.quartus_db" { Floorplan "D:/altera/shfrt/" "" "2.853 ns" { CLK REG8[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.853 ns" { CLK CLK~out0 REG8[0] } { 0.000ns 0.000ns 1.586ns } { 0.000ns 0.725ns 0.542ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" { } { { "../quartus51/shfrt.vhd" "" { Text "D:/altera/quartus51/shfrt.vhd" 13 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.216 ns + Longest register pin " "Info: + Longest register to pin delay is 5.216 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns REG8\[0\] 1 REG LC_X12_Y30_N3 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y30_N3; Fanout = 1; REG Node = 'REG8\[0\]'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shfrt" "UNKNOWN" "V1" "D:/altera/shfrt/db/shfrt.quartus_db" { Floorplan "D:/altera/shfrt/" "" "" { REG8[0] } "NODE_NAME" } "" } } { "../quartus51/shfrt.vhd" "" { Text "D:/altera/quartus51/shfrt.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.812 ns) + CELL(2.404 ns) 5.216 ns QB 2 PIN PIN_R15 0 " "Info: 2: + IC(2.812 ns) + CELL(2.404 ns) = 5.216 ns; Loc. = PIN_R15; Fanout = 0; PIN Node = 'QB'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shfrt" "UNKNOWN" "V1" "D:/altera/shfrt/db/shfrt.quartus_db" { Floorplan "D:/altera/shfrt/" "" "5.216 ns" { REG8[0] QB } "NODE_NAME" } "" } } { "../quartus51/shfrt.vhd" "" { Text "D:/altera/quartus51/shfrt.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.404 ns ( 46.09 % ) " "Info: Total cell delay = 2.404 ns ( 46.09 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.812 ns ( 53.91 % ) " "Info: Total interconnect delay = 2.812 ns ( 53.91 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shfrt" "UNKNOWN" "V1" "D:/altera/shfrt/db/shfrt.quartus_db" { Floorplan "D:/altera/shfrt/" "" "5.216 ns" { REG8[0] QB } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.216 ns" { REG8[0] QB } { 0.000ns 2.812ns } { 0.000ns 2.404ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shfrt" "UNKNOWN" "V1" "D:/altera/shfrt/db/shfrt.quartus_db" { Floorplan "D:/altera/shfrt/" "" "2.853 ns" { CLK REG8[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.853 ns" { CLK CLK~out0 REG8[0] } { 0.000ns 0.000ns 1.586ns } { 0.000ns 0.725ns 0.542ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shfrt" "UNKNOWN" "V1" "D:/altera/shfrt/db/shfrt.quartus_db" { Floorplan "D:/altera/shfrt/" "" "5.216 ns" { REG8[0] QB } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.216 ns" { REG8[0] QB } { 0.000ns 2.812ns } { 0.000ns 2.404ns } } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "REG8\[0\] DIN\[0\] CLK -2.024 ns register " "Info: th for register \"REG8\[0\]\" (data pin = \"DIN\[0\]\", clock pin = \"CLK\") is -2.024 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.853 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 2.853 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns CLK 1 CLK PIN_L2 8 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 8; CLK Node = 'CLK'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shfrt" "UNKNOWN" "V1" "D:/altera/shfrt/db/shfrt.quartus_db" { Floorplan "D:/altera/shfrt/" "" "" { CLK } "NODE_NAME" } "" } } { "../quartus51/shfrt.vhd" "" { Text "D:/altera/quartus51/shfrt.vhd" 4 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.586 ns) + CELL(0.542 ns) 2.853 ns REG8\[0\] 2 REG LC_X12_Y30_N3 1 " "Info: 2: + IC(1.586 ns) + CELL(0.542 ns) = 2.853 ns; Loc. = LC_X12_Y30_N3; Fanout = 1; REG Node = 'REG8\[0\]'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shfrt" "UNKNOWN" "V1" "D:/altera/shfrt/db/shfrt.quartus_db" { Floorplan "D:/altera/shfrt/" "" "2.128 ns" { CLK REG8[0] } "NODE_NAME" } "" } } { "../quartus51/shfrt.vhd" "" { Text "D:/altera/quartus51/shfrt.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns ( 44.41 % ) " "Info: Total cell delay = 1.267 ns ( 44.41 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.586 ns ( 55.59 % ) " "Info: Total interconnect delay = 1.586 ns ( 55.59 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shfrt" "UNKNOWN" "V1" "D:/altera/shfrt/db/shfrt.quartus_db" { Floorplan "D:/altera/shfrt/" "" "2.853 ns" { CLK REG8[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.853 ns" { CLK CLK~out0 REG8[0] } { 0.000ns 0.000ns 1.586ns } { 0.000ns 0.725ns 0.542ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" { } { { "../quartus51/shfrt.vhd" "" { Text "D:/altera/quartus51/shfrt.vhd" 13 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.977 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.977 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns DIN\[0\] 1 PIN PIN_K16 1 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_K16; Fanout = 1; PIN Node = 'DIN\[0\]'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shfrt" "UNKNOWN" "V1" "D:/altera/shfrt/db/shfrt.quartus_db" { Floorplan "D:/altera/shfrt/" "" "" { DIN[0] } "NODE_NAME" } "" } } { "../quartus51/shfrt.vhd" "" { Text "D:/altera/quartus51/shfrt.vhd" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.667 ns) + CELL(0.223 ns) 4.977 ns REG8\[0\] 2 REG LC_X12_Y30_N3 1 " "Info: 2: + IC(3.667 ns) + CELL(0.223 ns) = 4.977 ns; Loc. = LC_X12_Y30_N3; Fanout = 1; REG Node = 'REG8\[0\]'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shfrt" "UNKNOWN" "V1" "D:/altera/shfrt/db/shfrt.quartus_db" { Floorplan "D:/altera/shfrt/" "" "3.890 ns" { DIN[0] REG8[0] } "NODE_NAME" } "" } } { "../quartus51/shfrt.vhd" "" { Text "D:/altera/quartus51/shfrt.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.310 ns ( 26.32 % ) " "Info: Total cell delay = 1.310 ns ( 26.32 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.667 ns ( 73.68 % ) " "Info: Total interconnect delay = 3.667 ns ( 73.68 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shfrt" "UNKNOWN" "V1" "D:/altera/shfrt/db/shfrt.quartus_db" { Floorplan "D:/altera/shfrt/" "" "4.977 ns" { DIN[0] REG8[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "4.977 ns" { DIN[0] DIN[0]~out0 REG8[0] } { 0.000ns 0.000ns 3.667ns } { 0.000ns 1.087ns 0.223ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shfrt" "UNKNOWN" "V1" "D:/altera/shfrt/db/shfrt.quartus_db" { Floorplan "D:/altera/shfrt/" "" "2.853 ns" { CLK REG8[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.853 ns" { CLK CLK~out0 REG8[0] } { 0.000ns 0.000ns 1.586ns } { 0.000ns 0.725ns 0.542ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shfrt" "UNKNOWN" "V1" "D:/altera/shfrt/db/shfrt.quartus_db" { Floorplan "D:/altera/shfrt/" "" "4.977 ns" { DIN[0] REG8[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "4.977 ns" { DIN[0] DIN[0]~out0 REG8[0] } { 0.000ns 0.000ns 3.667ns } { 0.000ns 1.087ns 0.223ns } } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
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