shfrt.fit.qmsg

改程序的设计的是带有并行置位的移位寄存器

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue May 05 14:14:21 2009 " "Info: Processing started: Tue May 05 14:14:21 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off shfrt -c shfrt " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off shfrt -c shfrt" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IMPP_MPP_AUTO_ASSIGNED_DEVICE" "shfrt EP1S10F484C5 " "Info: Automatically selected device EP1S10F484C5 for design shfrt" {  } {  } 0 0 "Automatically selected device %2!s! for design %1!s!" 0 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1S20F484C5 " "Info: Device EP1S20F484C5 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0}
{ "Info" "IFSAC_FSAC_PINS_MISSING_LOCATION_INFO" "11 11 " "Info: No exact pin location assignment(s) for 11 pins of 11 total pins" { { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "QB " "Info: Pin QB not assigned to an exact location on the device" {  } { { "../quartus51/shfrt.vhd" "" { Text "D:/altera/quartus51/shfrt.vhd" 6 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "QB" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shfrt" "UNKNOWN" "V1" "D:/altera/shfrt/db/shfrt.quartus_db" { Floorplan "D:/altera/shfrt/" "" "" { QB } "NODE_NAME" } "" } } { "D:/altera/shfrt/shfrt.fld" "" { Floorplan "D:/altera/shfrt/shfrt.fld" "" "" { QB } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "DIN\[0\] " "Info: Pin DIN\[0\] not assigned to an exact location on the device" {  } { { "../quartus51/shfrt.vhd" "" { Text "D:/altera/quartus51/shfrt.vhd" 5 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "DIN\[0\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shfrt" "UNKNOWN" "V1" "D:/altera/shfrt/db/shfrt.quartus_db" { Floorplan "D:/altera/shfrt/" "" "" { DIN[0] } "NODE_NAME" } "" } } { "D:/altera/shfrt/shfrt.fld" "" { Floorplan "D:/altera/shfrt/shfrt.fld" "" "" { DIN[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "LOAD " "Info: Pin LOAD not assigned to an exact location on the device" {  } { { "../quartus51/shfrt.vhd" "" { Text "D:/altera/quartus51/shfrt.vhd" 4 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "LOAD" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shfrt" "UNKNOWN" "V1" "D:/altera/shfrt/db/shfrt.quartus_db" { Floorplan "D:/altera/shfrt/" "" "" { LOAD } "NODE_NAME" } "" } } { "D:/altera/shfrt/shfrt.fld" "" { Floorplan "D:/altera/shfrt/shfrt.fld" "" "" { LOAD } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "CLK " "Info: Pin CLK not assigned to an exact location on the device" {  } { { "../quartus51/shfrt.vhd" "" { Text "D:/altera/quartus51/shfrt.vhd" 4 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shfrt" "UNKNOWN" "V1" "D:/altera/shfrt/db/shfrt.quartus_db" { Floorplan "D:/altera/shfrt/" "" "" { CLK } "NODE_NAME" } "" } } { "D:/altera/shfrt/shfrt.fld" "" { Floorplan "D:/altera/shfrt/shfrt.fld" "" "" { CLK } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "DIN\[1\] " "Info: Pin DIN\[1\] not assigned to an exact location on the device" {  } { { "../quartus51/shfrt.vhd" "" { Text "D:/altera/quartus51/shfrt.vhd" 5 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "DIN\[1\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shfrt" "UNKNOWN" "V1" "D:/altera/shfrt/db/shfrt.quartus_db" { Floorplan "D:/altera/shfrt/" "" "" { DIN[1] } "NODE_NAME" } "" } } { "D:/altera/shfrt/shfrt.fld" "" { Floorplan "D:/altera/shfrt/shfrt.fld" "" "" { DIN[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "DIN\[2\] " "Info: Pin DIN\[2\] not assigned to an exact location on the device" {  } { { "../quartus51/shfrt.vhd" "" { Text "D:/altera/quartus51/shfrt.vhd" 5 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "DIN\[2\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shfrt" "UNKNOWN" "V1" "D:/altera/shfrt/db/shfrt.quartus_db" { Floorplan "D:/altera/shfrt/" "" "" { DIN[2] } "NODE_NAME" } "" } } { "D:/altera/shfrt/shfrt.fld" "" { Floorplan "D:/altera/shfrt/shfrt.fld" "" "" { DIN[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "DIN\[3\] " "Info: Pin DIN\[3\] not assigned to an exact location on the device" {  } { { "../quartus51/shfrt.vhd" "" { Text "D:/altera/quartus51/shfrt.vhd" 5 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "DIN\[3\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shfrt" "UNKNOWN" "V1" "D:/altera/shfrt/db/shfrt.quartus_db" { Floorplan "D:/altera/shfrt/" "" "" { DIN[3] } "NODE_NAME" } "" } } { "D:/altera/shfrt/shfrt.fld" "" { Floorplan "D:/altera/shfrt/shfrt.fld" "" "" { DIN[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "DIN\[4\] " "Info: Pin DIN\[4\] not assigned to an exact location on the device" {  } { { "../quartus51/shfrt.vhd" "" { Text "D:/altera/quartus51/shfrt.vhd" 5 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "DIN\[4\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shfrt" "UNKNOWN" "V1" "D:/altera/shfrt/db/shfrt.quartus_db" { Floorplan "D:/altera/shfrt/" "" "" { DIN[4] } "NODE_NAME" } "" } } { "D:/altera/shfrt/shfrt.fld" "" { Floorplan "D:/altera/shfrt/shfrt.fld" "" "" { DIN[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "DIN\[5\] " "Info: Pin DIN\[5\] not assigned to an exact location on the device" {  } { { "../quartus51/shfrt.vhd" "" { Text "D:/altera/quartus51/shfrt.vhd" 5 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "DIN\[5\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shfrt" "UNKNOWN" "V1" "D:/altera/shfrt/db/shfrt.quartus_db" { Floorplan "D:/altera/shfrt/" "" "" { DIN[5] } "NODE_NAME" } "" } } { "D:/altera/shfrt/shfrt.fld" "" { Floorplan "D:/altera/shfrt/shfrt.fld" "" "" { DIN[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "DIN\[6\] " "Info: Pin DIN\[6\] not assigned to an exact location on the device" {  } { { "../quartus51/shfrt.vhd" "" { Text "D:/altera/quartus51/shfrt.vhd" 5 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "DIN\[6\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shfrt" "UNKNOWN" "V1" "D:/altera/shfrt/db/shfrt.quartus_db" { Floorplan "D:/altera/shfrt/" "" "" { DIN[6] } "NODE_NAME" } "" } } { "D:/altera/shfrt/shfrt.fld" "" { Floorplan "D:/altera/shfrt/shfrt.fld" "" "" { DIN[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "DIN\[7\] " "Info: Pin DIN\[7\] not assigned to an exact location on the device" {  } { { "../quartus51/shfrt.vhd" "" { Text "D:/altera/quartus51/shfrt.vhd" 5 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "DIN\[7\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "shfrt" "UNKNOWN" "V1" "D:/altera/shfrt/db/shfrt.quartus_db" { Floorplan "D:/altera/shfrt/" "" "" { DIN[7] } "NODE_NAME" } "" } } { "D:/altera/shfrt/shfrt.fld" "" { Floorplan "D:/altera/shfrt/shfrt.fld" "" "" { DIN[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0}  } {  } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0}  } {  } 0 0 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0 0 "Performing register packing on registers with non-logic cell location assignments" 0 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0 0 "Completed register packing on registers with non-logic cell location assignments" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "CLK Global clock in PIN L2 " "Info: Automatically promoted signal \"CLK\" to use Global clock in PIN L2" {  } { { "../quartus51/shfrt.vhd" "" { Text "D:/altera/quartus51/shfrt.vhd" 4 -1 0 } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0 0 "Started Fast Input/Output/OE register processing" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0 0 "Finished Fast Input/Output/OE register processing" 0 0}
{ "Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Info: Start inferring scan chains for DSP blocks" {  } {  } 0 0 "Start inferring scan chains for DSP blocks" 0 0}
{ "Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Info: Inferring scan chains for DSP blocks is complete" {  } {  } 0 0 "Inferring scan chains for DSP blocks is complete" 0 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0 0 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0}
{ "Info" "IFSAC_FSAC_START_LUT_IO_MAC_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, RAM blocks, and DSP blocks to improve timing and density" {  } {  } 0 0 "Moving registers into I/O cells, LUTs, RAM blocks, and DSP blocks to improve timing and density" 0 0}