📄 shfrt.vho

📁 改程序的设计的是带有并行置位的移位寄存器
💻 VHO
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	oe => GND,
	outclk => GND,
	outclkena => VCC,
	inclk => GND,
	inclkena => VCC,
	areset => GND,
	sreset => GND,
	delayctrlin => GND,
	modesel => \DIN[7]~I_modesel\,
	combout => \DIN[7]~combout\,
	padio => ww_DIN(7));

\REG8[7]~I\ : stratix_lcell
-- Equation(s):
-- \REG8[7]\ = DFFEAS(\LOAD~combout\ & \DIN[7]~combout\ # !\LOAD~combout\ & (\REG8[7]\), GLOBAL(\CLK~combout\), VCC, , , , , , )

-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "normal",
--	synch_mode => "off",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	lut_mask => "CFC0",
--	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	pathsel => \REG8[7]~I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => \CLK~combout\,
	dataa => VCC,
	datab => \DIN[7]~combout\,
	datac => \LOAD~combout\,
	datad => \REG8[7]\,
	aclr => GND,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => \REG8[7]~I_modesel\,
	regout => \REG8[7]\);

\REG8[6]~I\ : stratix_lcell
-- Equation(s):
-- \REG8[6]\ = DFFEAS(\LOAD~combout\ & \DIN[6]~combout\ # !\LOAD~combout\ & (\REG8[7]\), GLOBAL(\CLK~combout\), VCC, , , , , , )

-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "normal",
--	synch_mode => "off",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	lut_mask => "CFC0",
--	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	pathsel => \REG8[6]~I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => \CLK~combout\,
	dataa => VCC,
	datab => \DIN[6]~combout\,
	datac => \LOAD~combout\,
	datad => \REG8[7]\,
	aclr => GND,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => \REG8[6]~I_modesel\,
	regout => \REG8[6]\);

\DIN[5]~I\ : stratix_io
-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "input",
--	ddio_mode => "none",
--	input_register_mode => "none",
--	output_register_mode => "none",
--	oe_register_mode => "none",
--	input_async_reset => "none",
--	output_async_reset => "none",
--	oe_async_reset => "none",
--	input_sync_reset => "none",
--	output_sync_reset => "none",
--	oe_sync_reset => "none",
--	input_power_up => "low",
--	output_power_up => "low",
--	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => GND,
	ddiodatain => GND,
	oe => GND,
	outclk => GND,
	outclkena => VCC,
	inclk => GND,
	inclkena => VCC,
	areset => GND,
	sreset => GND,
	delayctrlin => GND,
	modesel => \DIN[5]~I_modesel\,
	combout => \DIN[5]~combout\,
	padio => ww_DIN(5));

\REG8[5]~I\ : stratix_lcell
-- Equation(s):
-- \REG8[5]\ = DFFEAS(\LOAD~combout\ & (\DIN[5]~combout\) # !\LOAD~combout\ & \REG8[6]\, GLOBAL(\CLK~combout\), VCC, , , , , , )

-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "normal",
--	synch_mode => "off",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	lut_mask => "CACA",
--	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	pathsel => \REG8[5]~I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => \CLK~combout\,
	dataa => \REG8[6]\,
	datab => \DIN[5]~combout\,
	datac => \LOAD~combout\,
	datad => VCC,
	aclr => GND,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => \REG8[5]~I_modesel\,
	regout => \REG8[5]\);

\DIN[4]~I\ : stratix_io
-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "input",
--	ddio_mode => "none",
--	input_register_mode => "none",
--	output_register_mode => "none",
--	oe_register_mode => "none",
--	input_async_reset => "none",
--	output_async_reset => "none",
--	oe_async_reset => "none",
--	input_sync_reset => "none",
--	output_sync_reset => "none",
--	oe_sync_reset => "none",
--	input_power_up => "low",
--	output_power_up => "low",
--	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => GND,
	ddiodatain => GND,
	oe => GND,
	outclk => GND,
	outclkena => VCC,
	inclk => GND,
	inclkena => VCC,
	areset => GND,
	sreset => GND,
	delayctrlin => GND,
	modesel => \DIN[4]~I_modesel\,
	combout => \DIN[4]~combout\,
	padio => ww_DIN(4));

\REG8[4]~I\ : stratix_lcell
-- Equation(s):
-- \REG8[4]\ = DFFEAS(\LOAD~combout\ & (\DIN[4]~combout\) # !\LOAD~combout\ & \REG8[5]\, GLOBAL(\CLK~combout\), VCC, , , , , , )

-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "normal",
--	synch_mode => "off",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	lut_mask => "FC0C",
--	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	pathsel => \REG8[4]~I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => \CLK~combout\,
	dataa => VCC,
	datab => \REG8[5]\,
	datac => \LOAD~combout\,
	datad => \DIN[4]~combout\,
	aclr => GND,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => \REG8[4]~I_modesel\,
	regout => \REG8[4]\);

\REG8[3]~I\ : stratix_lcell
-- Equation(s):
-- \REG8[3]\ = DFFEAS(\LOAD~combout\ & \DIN[3]~combout\ # !\LOAD~combout\ & (\REG8[4]\), GLOBAL(\CLK~combout\), VCC, , , , , , )

-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "normal",
--	synch_mode => "off",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	lut_mask => "AFA0",
--	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	pathsel => \REG8[3]~I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => \CLK~combout\,
	dataa => \DIN[3]~combout\,
	datab => VCC,
	datac => \LOAD~combout\,
	datad => \REG8[4]\,
	aclr => GND,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => \REG8[3]~I_modesel\,
	regout => \REG8[3]\);

\REG8[2]~I\ : stratix_lcell
-- Equation(s):
-- \REG8[2]\ = DFFEAS(\LOAD~combout\ & \DIN[2]~combout\ # !\LOAD~combout\ & (\REG8[3]\), GLOBAL(\CLK~combout\), VCC, , , , , , )

-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "normal",
--	synch_mode => "off",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	lut_mask => "AFA0",
--	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	pathsel => \REG8[2]~I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => \CLK~combout\,
	dataa => \DIN[2]~combout\,
	datab => VCC,
	datac => \LOAD~combout\,
	datad => \REG8[3]\,
	aclr => GND,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => \REG8[2]~I_modesel\,
	regout => \REG8[2]\);

\REG8[1]~I\ : stratix_lcell
-- Equation(s):
-- \REG8[1]\ = DFFEAS(\LOAD~combout\ & \DIN[1]~combout\ # !\LOAD~combout\ & (\REG8[2]\), GLOBAL(\CLK~combout\), VCC, , , , , , )

-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "normal",
--	synch_mode => "off",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	lut_mask => "CFC0",
--	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	pathsel => \REG8[1]~I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => \CLK~combout\,
	dataa => VCC,
	datab => \DIN[1]~combout\,
	datac => \LOAD~combout\,
	datad => \REG8[2]\,
	aclr => GND,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => \REG8[1]~I_modesel\,
	regout => \REG8[1]\);

\DIN[0]~I\ : stratix_io
-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "input",
--	ddio_mode => "none",
--	input_register_mode => "none",
--	output_register_mode => "none",
--	oe_register_mode => "none",
--	input_async_reset => "none",
--	output_async_reset => "none",
--	oe_async_reset => "none",
--	input_sync_reset => "none",
--	output_sync_reset => "none",
--	oe_sync_reset => "none",
--	input_power_up => "low",
--	output_power_up => "low",
--	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => GND,
	ddiodatain => GND,
	oe => GND,
	outclk => GND,
	outclkena => VCC,
	inclk => GND,
	inclkena => VCC,
	areset => GND,
	sreset => GND,
	delayctrlin => GND,
	modesel => \DIN[0]~I_modesel\,
	combout => \DIN[0]~combout\,
	padio => ww_DIN(0));

\REG8[0]~I\ : stratix_lcell
-- Equation(s):
-- \REG8[0]\ = DFFEAS(\LOAD~combout\ & (\DIN[0]~combout\) # !\LOAD~combout\ & \REG8[1]\, GLOBAL(\CLK~combout\), VCC, , , , , , )

-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "normal",
--	synch_mode => "off",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	lut_mask => "FC0C",
--	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	pathsel => \REG8[0]~I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => \CLK~combout\,
	dataa => VCC,
	datab => \REG8[1]\,
	datac => \LOAD~combout\,
	datad => \DIN[0]~combout\,
	aclr => GND,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => \REG8[0]~I_modesel\,
	regout => \REG8[0]\);

\QB~I\ : stratix_io
-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "output",
--	ddio_mode => "none",
--	input_register_mode => "none",
--	output_register_mode => "none",
--	oe_register_mode => "none",
--	input_async_reset => "none",
--	output_async_reset => "none",
--	oe_async_reset => "none",
--	input_sync_reset => "none",
--	output_sync_reset => "none",
--	oe_sync_reset => "none",
--	input_power_up => "low",
--	output_power_up => "low",
--	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => \REG8[0]\,
	ddiodatain => GND,
	oe => VCC,
	outclk => GND,
	outclkena => VCC,
	inclk => GND,
	inclkena => VCC,
	areset => GND,
	sreset => GND,
	delayctrlin => GND,
	modesel => \QB~I_modesel\,
	padio => ww_QB);
END structure;
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