shfrt.vho

改程序的设计的是带有并行置位的移位寄存器

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II"
-- VERSION "Version 5.1 Build 176 10/26/2005 SJ Full Version"

-- DATE "05/05/2009 14:14:38"

-- 
-- Device: Altera EP1S10F484C5 Package FBGA484
-- 

-- 
-- This VHDL file should be used for PRIMETIME only
-- 

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

ENTITY 	SHFRT IS
    PORT (
	CLK : IN std_logic;
	LOAD : IN std_logic;
	DIN : IN std_logic_vector(7 DOWNTO 0);
	QB : OUT std_logic
	);
END SHFRT;

ARCHITECTURE structure OF SHFRT IS
SIGNAL GNDs : std_logic_vector(1024 DOWNTO 0);
SIGNAL VCCs : std_logic_vector(1024 DOWNTO 0);
SIGNAL gnd : std_logic;
SIGNAL vcc : std_logic;
SIGNAL lcell_ff_enable_asynch_arcs_out : std_logic;
SIGNAL ww_CLK : std_logic;
SIGNAL ww_LOAD : std_logic;
SIGNAL ww_DIN : std_logic_vector(7 DOWNTO 0);
SIGNAL ww_QB : std_logic;
SIGNAL \CLK~I_modesel\ : std_logic_vector(27 DOWNTO 0);
SIGNAL \DIN[1]~I_modesel\ : std_logic_vector(27 DOWNTO 0);
SIGNAL \LOAD~I_modesel\ : std_logic_vector(27 DOWNTO 0);
SIGNAL \DIN[2]~I_modesel\ : std_logic_vector(27 DOWNTO 0);
SIGNAL \DIN[3]~I_modesel\ : std_logic_vector(27 DOWNTO 0);
SIGNAL \DIN[6]~I_modesel\ : std_logic_vector(27 DOWNTO 0);
SIGNAL \DIN[7]~I_modesel\ : std_logic_vector(27 DOWNTO 0);
SIGNAL \REG8[7]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \REG8[7]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \REG8[6]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \REG8[6]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \DIN[5]~I_modesel\ : std_logic_vector(27 DOWNTO 0);
SIGNAL \REG8[5]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \REG8[5]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \DIN[4]~I_modesel\ : std_logic_vector(27 DOWNTO 0);
SIGNAL \REG8[4]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \REG8[4]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \REG8[3]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \REG8[3]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \REG8[2]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \REG8[2]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \REG8[1]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \REG8[1]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \DIN[0]~I_modesel\ : std_logic_vector(27 DOWNTO 0);
SIGNAL \REG8[0]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \REG8[0]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \QB~I_modesel\ : std_logic_vector(27 DOWNTO 0);
SIGNAL \CLK~combout\ : std_logic;
SIGNAL \DIN[1]~combout\ : std_logic;
SIGNAL \LOAD~combout\ : std_logic;
SIGNAL \DIN[2]~combout\ : std_logic;
SIGNAL \DIN[3]~combout\ : std_logic;
SIGNAL \DIN[6]~combout\ : std_logic;
SIGNAL \DIN[7]~combout\ : std_logic;
SIGNAL \REG8[7]\ : std_logic;
SIGNAL \REG8[6]\ : std_logic;
SIGNAL \DIN[5]~combout\ : std_logic;
SIGNAL \REG8[5]\ : std_logic;
SIGNAL \DIN[4]~combout\ : std_logic;
SIGNAL \REG8[4]\ : std_logic;
SIGNAL \REG8[3]\ : std_logic;
SIGNAL \REG8[2]\ : std_logic;
SIGNAL \REG8[1]\ : std_logic;
SIGNAL \DIN[0]~combout\ : std_logic;
SIGNAL \REG8[0]\ : std_logic;
COMPONENT stratix_lcell
PORT (
	clk : IN STD_LOGIC;
	dataa : IN STD_LOGIC;
	datab : IN STD_LOGIC;
	datac : IN STD_LOGIC;
	datad : IN STD_LOGIC;
	aclr : IN STD_LOGIC;
	aload : IN STD_LOGIC;
	sclr : IN STD_LOGIC;
	sload : IN STD_LOGIC;
	ena : IN STD_LOGIC;
	cin : IN STD_LOGIC;
	cin0 : IN STD_LOGIC;
	cin1 : IN STD_LOGIC;
	inverta : IN STD_LOGIC;
	regcascin : IN STD_LOGIC;
	combout : OUT STD_LOGIC;
	regout : OUT STD_LOGIC;
	cout : OUT STD_LOGIC;
	cout0 : OUT STD_LOGIC;
	cout1 : OUT STD_LOGIC;
	modesel : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
	pathsel : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
	enable_asynch_arcs : IN STD_LOGIC);
END COMPONENT;

COMPONENT stratix_io
PORT (
	datain : IN STD_LOGIC;
	ddiodatain : IN STD_LOGIC;
	oe : IN STD_LOGIC;
	outclk : IN STD_LOGIC;
	outclkena : IN STD_LOGIC;
	inclk : IN STD_LOGIC;
	inclkena : IN STD_LOGIC;
	areset : IN STD_LOGIC;
	sreset : IN STD_LOGIC;
	delayctrlin : IN STD_LOGIC;
	combout : OUT STD_LOGIC;
	regout : OUT STD_LOGIC;
	ddioregout : OUT STD_LOGIC;
	padio : INOUT STD_LOGIC;
	dqsundelayedout : OUT STD_LOGIC;
	modesel : IN STD_LOGIC_VECTOR(27 DOWNTO 0));
END COMPONENT;


COMPONENT INV
    PORT (
	IN1 : IN std_logic;
	Y :  OUT std_logic);
END COMPONENT;

COMPONENT AND1
    PORT (
	IN1 : IN std_logic;
	Y :  OUT std_logic);
END COMPONENT;
BEGIN

ww_CLK <= CLK;
ww_LOAD <= LOAD;
ww_DIN <= DIN;
QB <= ww_QB;

gnd <= '0';
vcc <= '1';
GNDs <= (OTHERS => '0');
VCCs <= (OTHERS => '1');

\CLK~I_modesel\ <= "0000000000000000000000000001";
\DIN[1]~I_modesel\ <= "0000000000000000000000000001";
\LOAD~I_modesel\ <= "0000000000000000000000000001";
\DIN[2]~I_modesel\ <= "0000000000000000000000000001";
\DIN[3]~I_modesel\ <= "0000000000000000000000000001";
\DIN[6]~I_modesel\ <= "0000000000000000000000000001";
\DIN[7]~I_modesel\ <= "0000000000000000000000000001";
\REG8[7]~I_modesel\ <= "1100001010101";
\REG8[7]~I_pathsel\ <= "00000001110";
\REG8[6]~I_modesel\ <= "1100001010101";
\REG8[6]~I_pathsel\ <= "00000001110";
\DIN[5]~I_modesel\ <= "0000000000000000000000000001";
\REG8[5]~I_modesel\ <= "1100001010101";
\REG8[5]~I_pathsel\ <= "00000000111";
\DIN[4]~I_modesel\ <= "0000000000000000000000000001";
\REG8[4]~I_modesel\ <= "1100001010101";
\REG8[4]~I_pathsel\ <= "00000001110";
\REG8[3]~I_modesel\ <= "1100001010101";
\REG8[3]~I_pathsel\ <= "00000001101";
\REG8[2]~I_modesel\ <= "1100001010101";
\REG8[2]~I_pathsel\ <= "00000001101";
\REG8[1]~I_modesel\ <= "1100001010101";
\REG8[1]~I_pathsel\ <= "00000001110";
\DIN[0]~I_modesel\ <= "0000000000000000000000000001";
\REG8[0]~I_modesel\ <= "1100001010101";
\REG8[0]~I_pathsel\ <= "00000001110";
\QB~I_modesel\ <= "0000000000000000000000000010";

lcell_ff_enable_asynch_arcs : AND1
PORT MAP (
	 IN1 => GND,
	 Y => lcell_ff_enable_asynch_arcs_out);

\CLK~I\ : stratix_io
-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "input",
--	ddio_mode => "none",
--	input_register_mode => "none",
--	output_register_mode => "none",
--	oe_register_mode => "none",
--	input_async_reset => "none",
--	output_async_reset => "none",
--	oe_async_reset => "none",
--	input_sync_reset => "none",
--	output_sync_reset => "none",
--	oe_sync_reset => "none",
--	input_power_up => "low",
--	output_power_up => "low",
--	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => GND,
	ddiodatain => GND,
	oe => GND,
	outclk => GND,
	outclkena => VCC,
	inclk => GND,
	inclkena => VCC,
	areset => GND,
	sreset => GND,
	delayctrlin => GND,
	modesel => \CLK~I_modesel\,
	combout => \CLK~combout\,
	padio => ww_CLK);

\DIN[1]~I\ : stratix_io
-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "input",
--	ddio_mode => "none",
--	input_register_mode => "none",
--	output_register_mode => "none",
--	oe_register_mode => "none",
--	input_async_reset => "none",
--	output_async_reset => "none",
--	oe_async_reset => "none",
--	input_sync_reset => "none",
--	output_sync_reset => "none",
--	oe_sync_reset => "none",
--	input_power_up => "low",
--	output_power_up => "low",
--	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => GND,
	ddiodatain => GND,
	oe => GND,
	outclk => GND,
	outclkena => VCC,
	inclk => GND,
	inclkena => VCC,
	areset => GND,
	sreset => GND,
	delayctrlin => GND,
	modesel => \DIN[1]~I_modesel\,
	combout => \DIN[1]~combout\,
	padio => ww_DIN(1));

\LOAD~I\ : stratix_io
-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "input",
--	ddio_mode => "none",
--	input_register_mode => "none",
--	output_register_mode => "none",
--	oe_register_mode => "none",
--	input_async_reset => "none",
--	output_async_reset => "none",
--	oe_async_reset => "none",
--	input_sync_reset => "none",
--	output_sync_reset => "none",
--	oe_sync_reset => "none",
--	input_power_up => "low",
--	output_power_up => "low",
--	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => GND,
	ddiodatain => GND,
	oe => GND,
	outclk => GND,
	outclkena => VCC,
	inclk => GND,
	inclkena => VCC,
	areset => GND,
	sreset => GND,
	delayctrlin => GND,
	modesel => \LOAD~I_modesel\,
	combout => \LOAD~combout\,
	padio => ww_LOAD);

\DIN[2]~I\ : stratix_io
-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "input",
--	ddio_mode => "none",
--	input_register_mode => "none",
--	output_register_mode => "none",
--	oe_register_mode => "none",
--	input_async_reset => "none",
--	output_async_reset => "none",
--	oe_async_reset => "none",
--	input_sync_reset => "none",
--	output_sync_reset => "none",
--	oe_sync_reset => "none",
--	input_power_up => "low",
--	output_power_up => "low",
--	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => GND,
	ddiodatain => GND,
	oe => GND,
	outclk => GND,
	outclkena => VCC,
	inclk => GND,
	inclkena => VCC,
	areset => GND,
	sreset => GND,
	delayctrlin => GND,
	modesel => \DIN[2]~I_modesel\,
	combout => \DIN[2]~combout\,
	padio => ww_DIN(2));

\DIN[3]~I\ : stratix_io
-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "input",
--	ddio_mode => "none",
--	input_register_mode => "none",
--	output_register_mode => "none",
--	oe_register_mode => "none",
--	input_async_reset => "none",
--	output_async_reset => "none",
--	oe_async_reset => "none",
--	input_sync_reset => "none",
--	output_sync_reset => "none",
--	oe_sync_reset => "none",
--	input_power_up => "low",
--	output_power_up => "low",
--	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => GND,
	ddiodatain => GND,
	oe => GND,
	outclk => GND,
	outclkena => VCC,
	inclk => GND,
	inclkena => VCC,
	areset => GND,
	sreset => GND,
	delayctrlin => GND,
	modesel => \DIN[3]~I_modesel\,
	combout => \DIN[3]~combout\,
	padio => ww_DIN(3));

\DIN[6]~I\ : stratix_io
-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "input",
--	ddio_mode => "none",
--	input_register_mode => "none",
--	output_register_mode => "none",
--	oe_register_mode => "none",
--	input_async_reset => "none",
--	output_async_reset => "none",
--	oe_async_reset => "none",
--	input_sync_reset => "none",
--	output_sync_reset => "none",
--	oe_sync_reset => "none",
--	input_power_up => "low",
--	output_power_up => "low",
--	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => GND,
	ddiodatain => GND,
	oe => GND,
	outclk => GND,
	outclkena => VCC,
	inclk => GND,
	inclkena => VCC,
	areset => GND,
	sreset => GND,
	delayctrlin => GND,
	modesel => \DIN[6]~I_modesel\,
	combout => \DIN[6]~combout\,
	padio => ww_DIN(6));

\DIN[7]~I\ : stratix_io
-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "input",
--	ddio_mode => "none",
--	input_register_mode => "none",
--	output_register_mode => "none",
--	oe_register_mode => "none",
--	input_async_reset => "none",
--	output_async_reset => "none",
--	oe_async_reset => "none",
--	input_sync_reset => "none",
--	output_sync_reset => "none",
--	oe_sync_reset => "none",
--	input_power_up => "low",
--	output_power_up => "low",
--	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => GND,
	ddiodatain => GND,