shfrt.map.eqn

来自「改程序的设计的是带有并行置位的移位寄存器」· EQN 代码 · 共 136 行

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--REG8[0] is REG8[0]
--operation mode is normal

REG8[0]_lut_out = LOAD & DIN[0] # !LOAD & (REG8[1]);
REG8[0] = DFFEAS(REG8[0]_lut_out, CLK, VCC, , , , , , );


--REG8[1] is REG8[1]
--operation mode is normal

REG8[1]_lut_out = LOAD & DIN[1] # !LOAD & (REG8[2]);
REG8[1] = DFFEAS(REG8[1]_lut_out, CLK, VCC, , , , , , );


--REG8[2] is REG8[2]
--operation mode is normal

REG8[2]_lut_out = LOAD & DIN[2] # !LOAD & (REG8[3]);
REG8[2] = DFFEAS(REG8[2]_lut_out, CLK, VCC, , , , , , );


--REG8[3] is REG8[3]
--operation mode is normal

REG8[3]_lut_out = LOAD & DIN[3] # !LOAD & (REG8[4]);
REG8[3] = DFFEAS(REG8[3]_lut_out, CLK, VCC, , , , , , );


--REG8[4] is REG8[4]
--operation mode is normal

REG8[4]_lut_out = LOAD & DIN[4] # !LOAD & (REG8[5]);
REG8[4] = DFFEAS(REG8[4]_lut_out, CLK, VCC, , , , , , );


--REG8[5] is REG8[5]
--operation mode is normal

REG8[5]_lut_out = LOAD & DIN[5] # !LOAD & (REG8[6]);
REG8[5] = DFFEAS(REG8[5]_lut_out, CLK, VCC, , , , , , );


--REG8[6] is REG8[6]
--operation mode is normal

REG8[6]_lut_out = LOAD & DIN[6] # !LOAD & (REG8[7]);
REG8[6] = DFFEAS(REG8[6]_lut_out, CLK, VCC, , , , , , );


--REG8[7] is REG8[7]
--operation mode is normal

REG8[7]_lut_out = LOAD & DIN[7] # !LOAD & (REG8[7]);
REG8[7] = DFFEAS(REG8[7]_lut_out, CLK, VCC, , , , , , );


--DIN[0] is DIN[0]
--operation mode is input

DIN[0] = INPUT();


--LOAD is LOAD
--operation mode is input

LOAD = INPUT();


--CLK is CLK
--operation mode is input

CLK = INPUT();


--DIN[1] is DIN[1]
--operation mode is input

DIN[1] = INPUT();


--DIN[2] is DIN[2]
--operation mode is input

DIN[2] = INPUT();


--DIN[3] is DIN[3]
--operation mode is input

DIN[3] = INPUT();


--DIN[4] is DIN[4]
--operation mode is input

DIN[4] = INPUT();


--DIN[5] is DIN[5]
--operation mode is input

DIN[5] = INPUT();


--DIN[6] is DIN[6]
--operation mode is input

DIN[6] = INPUT();


--DIN[7] is DIN[7]
--operation mode is input

DIN[7] = INPUT();


--QB is QB
--operation mode is output

QB = OUTPUT(REG8[0]);