shfrt.tan.rpt

改程序的设计的是带有并行置位的移位寄存器

; N/A   ; None         ; 2.348 ns   ; LOAD   ; REG8[7] ; CLK      ;
; N/A   ; None         ; 2.346 ns   ; LOAD   ; REG8[2] ; CLK      ;
; N/A   ; None         ; 2.344 ns   ; LOAD   ; REG8[4] ; CLK      ;
; N/A   ; None         ; 2.341 ns   ; LOAD   ; REG8[0] ; CLK      ;
; N/A   ; None         ; 2.338 ns   ; LOAD   ; REG8[3] ; CLK      ;
; N/A   ; None         ; 2.141 ns   ; DIN[4] ; REG8[4] ; CLK      ;
; N/A   ; None         ; 2.134 ns   ; DIN[0] ; REG8[0] ; CLK      ;
+-------+--------------+------------+--------+---------+----------+


+---------------------------------------------------------------+
; tco                                                           ;
+-------+--------------+------------+---------+----+------------+
; Slack ; Required tco ; Actual tco ; From    ; To ; From Clock ;
+-------+--------------+------------+---------+----+------------+
; N/A   ; None         ; 8.225 ns   ; REG8[0] ; QB ; CLK        ;
+-------+--------------+------------+---------+----+------------+


+-----------------------------------------------------------------------+
; th                                                                    ;
+---------------+-------------+-----------+--------+---------+----------+
; Minimum Slack ; Required th ; Actual th ; From   ; To      ; To Clock ;
+---------------+-------------+-----------+--------+---------+----------+
; N/A           ; None        ; -2.024 ns ; DIN[0] ; REG8[0] ; CLK      ;
; N/A           ; None        ; -2.031 ns ; DIN[4] ; REG8[4] ; CLK      ;
; N/A           ; None        ; -2.228 ns ; LOAD   ; REG8[3] ; CLK      ;
; N/A           ; None        ; -2.231 ns ; LOAD   ; REG8[0] ; CLK      ;
; N/A           ; None        ; -2.234 ns ; LOAD   ; REG8[4] ; CLK      ;
; N/A           ; None        ; -2.236 ns ; LOAD   ; REG8[2] ; CLK      ;
; N/A           ; None        ; -2.238 ns ; LOAD   ; REG8[6] ; CLK      ;
; N/A           ; None        ; -2.238 ns ; LOAD   ; REG8[7] ; CLK      ;
; N/A           ; None        ; -2.239 ns ; LOAD   ; REG8[1] ; CLK      ;
; N/A           ; None        ; -2.240 ns ; LOAD   ; REG8[5] ; CLK      ;
; N/A           ; None        ; -2.266 ns ; DIN[1] ; REG8[1] ; CLK      ;
; N/A           ; None        ; -2.275 ns ; DIN[6] ; REG8[6] ; CLK      ;
; N/A           ; None        ; -2.363 ns ; DIN[2] ; REG8[2] ; CLK      ;
; N/A           ; None        ; -2.400 ns ; DIN[7] ; REG8[7] ; CLK      ;
; N/A           ; None        ; -2.421 ns ; DIN[5] ; REG8[5] ; CLK      ;
; N/A           ; None        ; -2.564 ns ; DIN[3] ; REG8[3] ; CLK      ;
+---------------+-------------+-----------+--------+---------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Tue May 05 14:14:35 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off shfrt -c shfrt --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
Info: Clock "CLK" Internal fmax is restricted to 422.12 MHz between source register "REG8[6]" and destination register "REG8[5]"
    Info: fmax restricted to clock pin edge rate 2.369 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.931 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y30_N7; Fanout = 1; REG Node = 'REG8[6]'
            Info: 2: + IC(0.392 ns) + CELL(0.539 ns) = 0.931 ns; Loc. = LC_X12_Y30_N5; Fanout = 1; REG Node = 'REG8[5]'
            Info: Total cell delay = 0.539 ns ( 57.89 % )
            Info: Total interconnect delay = 0.392 ns ( 42.11 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "CLK" to destination register is 2.853 ns
                Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 8; CLK Node = 'CLK'
                Info: 2: + IC(1.586 ns) + CELL(0.542 ns) = 2.853 ns; Loc. = LC_X12_Y30_N5; Fanout = 1; REG Node = 'REG8[5]'
                Info: Total cell delay = 1.267 ns ( 44.41 % )
                Info: Total interconnect delay = 1.586 ns ( 55.59 % )
            Info: - Longest clock path from clock "CLK" to source register is 2.853 ns
                Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 8; CLK Node = 'CLK'
                Info: 2: + IC(1.586 ns) + CELL(0.542 ns) = 2.853 ns; Loc. = LC_X12_Y30_N7; Fanout = 1; REG Node = 'REG8[6]'
                Info: Total cell delay = 1.267 ns ( 44.41 % )
                Info: Total interconnect delay = 1.586 ns ( 55.59 % )
        Info: + Micro clock to output delay of source is 0.156 ns
        Info: + Micro setup delay of destination is 0.010 ns
Info: tsu for register "REG8[3]" (data pin = "DIN[3]", clock pin = "CLK") is 2.674 ns
    Info: + Longest pin to register delay is 5.517 ns
        Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_E20; Fanout = 1; PIN Node = 'DIN[3]'
        Info: 2: + IC(3.744 ns) + CELL(0.539 ns) = 5.517 ns; Loc. = LC_X12_Y30_N2; Fanout = 1; REG Node = 'REG8[3]'
        Info: Total cell delay = 1.773 ns ( 32.14 % )
        Info: Total interconnect delay = 3.744 ns ( 67.86 % )
    Info: + Micro setup delay of destination is 0.010 ns
    Info: - Shortest clock path from clock "CLK" to destination register is 2.853 ns
        Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 8; CLK Node = 'CLK'
        Info: 2: + IC(1.586 ns) + CELL(0.542 ns) = 2.853 ns; Loc. = LC_X12_Y30_N2; Fanout = 1; REG Node = 'REG8[3]'
        Info: Total cell delay = 1.267 ns ( 44.41 % )
        Info: Total interconnect delay = 1.586 ns ( 55.59 % )
Info: tco from clock "CLK" to destination pin "QB" through register "REG8[0]" is 8.225 ns
    Info: + Longest clock path from clock "CLK" to source register is 2.853 ns
        Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 8; CLK Node = 'CLK'
        Info: 2: + IC(1.586 ns) + CELL(0.542 ns) = 2.853 ns; Loc. = LC_X12_Y30_N3; Fanout = 1; REG Node = 'REG8[0]'
        Info: Total cell delay = 1.267 ns ( 44.41 % )
        Info: Total interconnect delay = 1.586 ns ( 55.59 % )
    Info: + Micro clock to output delay of source is 0.156 ns
    Info: + Longest register to pin delay is 5.216 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y30_N3; Fanout = 1; REG Node = 'REG8[0]'
        Info: 2: + IC(2.812 ns) + CELL(2.404 ns) = 5.216 ns; Loc. = PIN_R15; Fanout = 0; PIN Node = 'QB'
        Info: Total cell delay = 2.404 ns ( 46.09 % )
        Info: Total interconnect delay = 2.812 ns ( 53.91 % )
Info: th for register "REG8[0]" (data pin = "DIN[0]", clock pin = "CLK") is -2.024 ns
    Info: + Longest clock path from clock "CLK" to destination register is 2.853 ns
        Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 8; CLK Node = 'CLK'
        Info: 2: + IC(1.586 ns) + CELL(0.542 ns) = 2.853 ns; Loc. = LC_X12_Y30_N3; Fanout = 1; REG Node = 'REG8[0]'
        Info: Total cell delay = 1.267 ns ( 44.41 % )
        Info: Total interconnect delay = 1.586 ns ( 55.59 % )
    Info: + Micro hold delay of destination is 0.100 ns
    Info: - Shortest pin to register delay is 4.977 ns
        Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_K16; Fanout = 1; PIN Node = 'DIN[0]'
        Info: 2: + IC(3.667 ns) + CELL(0.223 ns) = 4.977 ns; Loc. = LC_X12_Y30_N3; Fanout = 1; REG Node = 'REG8[0]'
        Info: Total cell delay = 1.310 ns ( 26.32 % )
        Info: Total interconnect delay = 3.667 ns ( 73.68 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Tue May 05 14:14:36 2009
    Info: Elapsed time: 00:00:01