shfrt.vho

改程序的设计的是带有并行置位的移位寄存器

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II"
-- VERSION "Version 5.1 Build 176 10/26/2005 SJ Full Version"

-- DATE "05/05/2009 14:14:38"

-- 
-- Device: Altera EP1S10F484C5 Package FBGA484
-- 

-- 
-- This VHDL file should be used for ModelSim (VHDL) only
-- 

LIBRARY IEEE, stratix;
USE IEEE.std_logic_1164.all;
USE stratix.stratix_components.all;

ENTITY 	SHFRT IS
    PORT (
	CLK : IN std_logic;
	LOAD : IN std_logic;
	DIN : IN std_logic_vector(7 DOWNTO 0);
	QB : OUT std_logic
	);
END SHFRT;

ARCHITECTURE structure OF SHFRT IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL devoe : std_logic := '0';
SIGNAL devclrn : std_logic := '1';
SIGNAL devpor : std_logic := '1';
SIGNAL ww_devoe : std_logic;
SIGNAL ww_devclrn : std_logic;
SIGNAL ww_devpor : std_logic;
SIGNAL ww_CLK : std_logic;
SIGNAL ww_LOAD : std_logic;
SIGNAL ww_DIN : std_logic_vector(7 DOWNTO 0);
SIGNAL ww_QB : std_logic;
SIGNAL \CLK~combout\ : std_logic;
SIGNAL \DIN[1]~combout\ : std_logic;
SIGNAL \LOAD~combout\ : std_logic;
SIGNAL \DIN[2]~combout\ : std_logic;
SIGNAL \DIN[3]~combout\ : std_logic;
SIGNAL \DIN[6]~combout\ : std_logic;
SIGNAL \DIN[7]~combout\ : std_logic;
SIGNAL \REG8[7]\ : std_logic;
SIGNAL \REG8[6]\ : std_logic;
SIGNAL \DIN[5]~combout\ : std_logic;
SIGNAL \REG8[5]\ : std_logic;
SIGNAL \DIN[4]~combout\ : std_logic;
SIGNAL \REG8[4]\ : std_logic;
SIGNAL \REG8[3]\ : std_logic;
SIGNAL \REG8[2]\ : std_logic;
SIGNAL \REG8[1]\ : std_logic;
SIGNAL \DIN[0]~combout\ : std_logic;
SIGNAL \REG8[0]\ : std_logic;

BEGIN

ww_CLK <= CLK;
ww_LOAD <= LOAD;
ww_DIN <= DIN;
QB <= ww_QB;
ww_devoe <= devoe;
ww_devclrn <= devclrn;
ww_devpor <= devpor;

\CLK~I\ : stratix_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	ddio_mode => "none",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_CLK,
	combout => \CLK~combout\);

\DIN[1]~I\ : stratix_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	ddio_mode => "none",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_DIN(1),
	combout => \DIN[1]~combout\);

\LOAD~I\ : stratix_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	ddio_mode => "none",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_LOAD,
	combout => \LOAD~combout\);

\DIN[2]~I\ : stratix_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	ddio_mode => "none",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_DIN(2),
	combout => \DIN[2]~combout\);

\DIN[3]~I\ : stratix_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	ddio_mode => "none",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_DIN(3),
	combout => \DIN[3]~combout\);

\DIN[6]~I\ : stratix_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	ddio_mode => "none",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_DIN(6),
	combout => \DIN[6]~combout\);

\DIN[7]~I\ : stratix_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	ddio_mode => "none",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_DIN(7),
	combout => \DIN[7]~combout\);

\REG8[7]~I\ : stratix_lcell
-- Equation(s):
-- \REG8[7]\ = DFFEAS(\LOAD~combout\ & \DIN[7]~combout\ # !\LOAD~combout\ & (\REG8[7]\), GLOBAL(\CLK~combout\), VCC, , , , , , )

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "CFC0",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => \CLK~combout\,
	datab => \DIN[7]~combout\,
	datac => \LOAD~combout\,
	datad => \REG8[7]\,
	aclr => GND,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \REG8[7]\);

\REG8[6]~I\ : stratix_lcell
-- Equation(s):
-- \REG8[6]\ = DFFEAS(\LOAD~combout\ & \DIN[6]~combout\ # !\LOAD~combout\ & (\REG8[7]\), GLOBAL(\CLK~combout\), VCC, , , , , , )

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "CFC0",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => \CLK~combout\,
	datab => \DIN[6]~combout\,
	datac => \LOAD~combout\,
	datad => \REG8[7]\,
	aclr => GND,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \REG8[6]\);

\DIN[5]~I\ : stratix_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	ddio_mode => "none",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_DIN(5),
	combout => \DIN[5]~combout\);

\REG8[5]~I\ : stratix_lcell
-- Equation(s):
-- \REG8[5]\ = DFFEAS(\LOAD~combout\ & (\DIN[5]~combout\) # !\LOAD~combout\ & \REG8[6]\, GLOBAL(\CLK~combout\), VCC, , , , , , )

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "CACA",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => \CLK~combout\,
	dataa => \REG8[6]\,
	datab => \DIN[5]~combout\,
	datac => \LOAD~combout\,
	aclr => GND,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \REG8[5]\);

\DIN[4]~I\ : stratix_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	ddio_mode => "none",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_DIN(4),
	combout => \DIN[4]~combout\);

\REG8[4]~I\ : stratix_lcell
-- Equation(s):
-- \REG8[4]\ = DFFEAS(\LOAD~combout\ & (\DIN[4]~combout\) # !\LOAD~combout\ & \REG8[5]\, GLOBAL(\CLK~combout\), VCC, , , , , , )

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "FC0C",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => \CLK~combout\,
	datab => \REG8[5]\,
	datac => \LOAD~combout\,
	datad => \DIN[4]~combout\,
	aclr => GND,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \REG8[4]\);

\REG8[3]~I\ : stratix_lcell
-- Equation(s):
-- \REG8[3]\ = DFFEAS(\LOAD~combout\ & \DIN[3]~combout\ # !\LOAD~combout\ & (\REG8[4]\), GLOBAL(\CLK~combout\), VCC, , , , , , )

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "AFA0",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => \CLK~combout\,
	dataa => \DIN[3]~combout\,
	datac => \LOAD~combout\,
	datad => \REG8[4]\,
	aclr => GND,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \REG8[3]\);

\REG8[2]~I\ : stratix_lcell
-- Equation(s):
-- \REG8[2]\ = DFFEAS(\LOAD~combout\ & \DIN[2]~combout\ # !\LOAD~combout\ & (\REG8[3]\), GLOBAL(\CLK~combout\), VCC, , , , , , )

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "AFA0",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => \CLK~combout\,
	dataa => \DIN[2]~combout\,
	datac => \LOAD~combout\,
	datad => \REG8[3]\,
	aclr => GND,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \REG8[2]\);

\REG8[1]~I\ : stratix_lcell
-- Equation(s):
-- \REG8[1]\ = DFFEAS(\LOAD~combout\ & \DIN[1]~combout\ # !\LOAD~combout\ & (\REG8[2]\), GLOBAL(\CLK~combout\), VCC, , , , , , )

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "CFC0",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => \CLK~combout\,
	datab => \DIN[1]~combout\,
	datac => \LOAD~combout\,
	datad => \REG8[2]\,
	aclr => GND,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \REG8[1]\);

\DIN[0]~I\ : stratix_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	ddio_mode => "none",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_DIN(0),
	combout => \DIN[0]~combout\);

\REG8[0]~I\ : stratix_lcell
-- Equation(s):
-- \REG8[0]\ = DFFEAS(\LOAD~combout\ & (\DIN[0]~combout\) # !\LOAD~combout\ & \REG8[1]\, GLOBAL(\CLK~combout\), VCC, , , , , , )

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "FC0C",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => \CLK~combout\,
	datab => \REG8[1]\,
	datac => \LOAD~combout\,
	datad => \DIN[0]~combout\,
	aclr => GND,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \REG8[0]\);

\QB~I\ : stratix_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "output",
	ddio_mode => "none",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => \REG8[0]\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => VCC,
	padio => ww_QB);
END structure;