📄 msp430x12x.h
字号:
#define UCTL0_ U0CTL_ /* USART 0 Control */
DEFC( UCTL0 , UCTL0_)
#define UTCTL0_ U0TCTL_ /* USART 0 Transmit Control */
DEFC( UTCTL0 , UTCTL0_)
#define URCTL0_ U0RCTL_ /* USART 0 Receive Control */
DEFC( URCTL0 , URCTL0_)
#define UMCTL0_ U0MCTL_ /* USART 0 Modulation Control */
DEFC( UMCTL0 , UMCTL0_)
#define UBR00_ U0BR0_ /* USART 0 Baud Rate 0 */
DEFC( UBR00 , UBR00_)
#define UBR10_ U0BR1_ /* USART 0 Baud Rate 1 */
DEFC( UBR10 , UBR10_)
#define RXBUF0_ U0RXBUF_ /* USART 0 Receive Buffer */
READ_ONLY DEFC( RXBUF0 , RXBUF0_)
#define TXBUF0_ U0TXBUF_ /* USART 0 Transmit Buffer */
DEFC( TXBUF0 , TXBUF0_)
#define UCTL_0_ U0CTL_ /* USART 0 Control */
DEFC( UCTL_0 , UCTL_0_)
#define UTCTL_0_ U0TCTL_ /* USART 0 Transmit Control */
DEFC( UTCTL_0 , UTCTL_0_)
#define URCTL_0_ U0RCTL_ /* USART 0 Receive Control */
DEFC( URCTL_0 , URCTL_0_)
#define UMCTL_0_ U0MCTL_ /* USART 0 Modulation Control */
DEFC( UMCTL_0 , UMCTL_0_)
#define UBR0_0_ U0BR0_ /* USART 0 Baud Rate 0 */
DEFC( UBR0_0 , UBR0_0_)
#define UBR1_0_ U0BR1_ /* USART 0 Baud Rate 1 */
DEFC( UBR1_0 , UBR1_0_)
#define RXBUF_0_ U0RXBUF_ /* USART 0 Receive Buffer */
READ_ONLY DEFC( RXBUF_0 , RXBUF_0_)
#define TXBUF_0_ U0TXBUF_ /* USART 0 Transmit Buffer */
DEFC( TXBUF_0 , TXBUF_0_)
/************************************************************
* Timer A
************************************************************/
#define TAIV_ (0x012E) /* Timer A Interrupt Vector Word */
READ_ONLY DEFW( TAIV , TAIV_)
#define TACTL_ (0x0160) /* Timer A Control */
DEFW( TACTL , TACTL_)
#define TACCTL0_ (0x0162) /* Timer A Capture/Compare Control 0 */
DEFW( TACCTL0 , TACCTL0_)
#define TACCTL1_ (0x0164) /* Timer A Capture/Compare Control 1 */
DEFW( TACCTL1 , TACCTL1_)
#define TACCTL2_ (0x0166) /* Timer A Capture/Compare Control 2 */
DEFW( TACCTL2 , TACCTL2_)
#define TAR_ (0x0170) /* Timer A */
DEFW( TAR , TAR_)
#define TACCR0_ (0x0172) /* Timer A Capture/Compare 0 */
DEFW( TACCR0 , TACCR0_)
#define TACCR1_ (0x0174) /* Timer A Capture/Compare 1 */
DEFW( TACCR1 , TACCR1_)
#define TACCR2_ (0x0176) /* Timer A Capture/Compare 2 */
DEFW( TACCR2 , TACCR2_)
/* Alternate register names */
#define CCTL0_ TACCTL0_ /* Timer A Capture/Compare Control 0 */
DEFW( CCTL0 , CCTL0_)
#define CCTL1_ TACCTL1_ /* Timer A Capture/Compare Control 1 */
DEFW( CCTL1 , CCTL1_)
#define CCTL2_ TACCTL2_ /* Timer A Capture/Compare Control 2 */
DEFW( CCTL2 , CCTL2_)
#define CCR0_ TACCR0_ /* Timer A Capture/Compare 0 */
DEFW( CCR0 , CCR0_)
#define CCR1_ TACCR1_ /* Timer A Capture/Compare 1 */
DEFW( CCR1 , CCR1_)
#define CCR2_ TACCR2_ /* Timer A Capture/Compare 2 */
DEFW( CCR2 , CCR2_)
#define TASSEL2 (0x0400) /* unused */ /* to distinguish from USART SSELx */
#define TASSEL1 (0x0200) /* Timer A clock source select 0 */
#define TASSEL0 (0x0100) /* Timer A clock source select 1 */
#define ID1 (0x0080) /* Timer A clock input devider 1 */
#define ID0 (0x0040) /* Timer A clock input devider 0 */
#define MC1 (0x0020) /* Timer A mode control 1 */
#define MC0 (0x0010) /* Timer A mode control 0 */
#define TACLR (0x0004) /* Timer A counter clear */
#define TAIE (0x0002) /* Timer A counter interrupt enable */
#define TAIFG (0x0001) /* Timer A counter interrupt flag */
#define MC_0 (0*0x10) /* Timer A mode control: 0 - Stop */
#define MC_1 (1*0x10) /* Timer A mode control: 1 - Up to CCR0 */
#define MC_2 (2*0x10) /* Timer A mode control: 2 - Continous up */
#define MC_3 (3*0x10) /* Timer A mode control: 3 - Up/Down */
#define ID_0 (0*0x40) /* Timer A input divider: 0 - /1 */
#define ID_1 (1*0x40) /* Timer A input divider: 1 - /2 */
#define ID_2 (2*0x40) /* Timer A input divider: 2 - /4 */
#define ID_3 (3*0x40) /* Timer A input divider: 3 - /8 */
#define TASSEL_0 (0*0x100) /* Timer A clock source select: 0 - TACLK */
#define TASSEL_1 (1*0x100) /* Timer A clock source select: 1 - ACLK */
#define TASSEL_2 (2*0x100) /* Timer A clock source select: 2 - SMCLK */
#define TASSEL_3 (3*0x100) /* Timer A clock source select: 3 - INCLK */
#define CM1 (0x8000) /* Capture mode 1 */
#define CM0 (0x4000) /* Capture mode 0 */
#define CCIS1 (0x2000) /* Capture input select 1 */
#define CCIS0 (0x1000) /* Capture input select 0 */
#define SCS (0x0800) /* Capture sychronize */
#define SCCI (0x0400) /* Latched capture signal (read) */
#define CAP (0x0100) /* Capture mode: 1 /Compare mode : 0 */
#define OUTMOD2 (0x0080) /* Output mode 2 */
#define OUTMOD1 (0x0040) /* Output mode 1 */
#define OUTMOD0 (0x0020) /* Output mode 0 */
#define CCIE (0x0010) /* Capture/compare interrupt enable */
#define CCI (0x0008) /* Capture input signal (read) */
#define OUT (0x0004) /* PWM Output signal if output mode 0 */
#define COV (0x0002) /* Capture/compare overflow flag */
#define CCIFG (0x0001) /* Capture/compare interrupt flag */
#define OUTMOD_0 (0*0x20) /* PWM output mode: 0 - output only */
#define OUTMOD_1 (1*0x20) /* PWM output mode: 1 - set */
#define OUTMOD_2 (2*0x20) /* PWM output mode: 2 - PWM toggle/reset */
#define OUTMOD_3 (3*0x20) /* PWM output mode: 3 - PWM set/reset */
#define OUTMOD_4 (4*0x20) /* PWM output mode: 4 - toggle */
#define OUTMOD_5 (5*0x20) /* PWM output mode: 5 - Reset */
#define OUTMOD_6 (6*0x20) /* PWM output mode: 6 - PWM toggle/set */
#define OUTMOD_7 (7*0x20) /* PWM output mode: 7 - PWM reset/set */
#define CCIS_0 (0*0x1000) /* Capture input select: 0 - CCIxA */
#define CCIS_1 (1*0x1000) /* Capture input select: 1 - CCIxB */
#define CCIS_2 (2*0x1000) /* Capture input select: 2 - GND */
#define CCIS_3 (3*0x1000) /* Capture input select: 3 - Vcc */
#define CM_0 (0*0x4000u) /* Capture mode: 0 - disabled */
#define CM_1 (1*0x4000u) /* Capture mode: 1 - pos. edge */
#define CM_2 (2*0x4000u) /* Capture mode: 1 - neg. edge */
#define CM_3 (3*0x4000u) /* Capture mode: 1 - both edges */
/************************************************************
* Basic Clock Module
************************************************************/
#define DCOCTL_ (0x0056) /* DCO Clock Frequency Control */
DEFC( DCOCTL , DCOCTL_)
#define BCSCTL1_ (0x0057) /* Basic Clock System Control 1 */
DEFC( BCSCTL1 , BCSCTL1_)
#define BCSCTL2_ (0x0058) /* Basic Clock System Control 2 */
DEFC( BCSCTL2 , BCSCTL2_)
#define MOD0 (0x01) /* Modulation Bit 0 */
#define MOD1 (0x02) /* Modulation Bit 1 */
#define MOD2 (0x04) /* Modulation Bit 2 */
#define MOD3 (0x08) /* Modulation Bit 3 */
#define MOD4 (0x10) /* Modulation Bit 4 */
#define DCO0 (0x20) /* DCO Select Bit 0 */
#define DCO1 (0x40) /* DCO Select Bit 1 */
#define DCO2 (0x80) /* DCO Select Bit 2 */
#define RSEL0 (0x01) /* Resistor Select Bit 0 */
#define RSEL1 (0x02) /* Resistor Select Bit 1 */
#define RSEL2 (0x04) /* Resistor Select Bit 2 */
#define XT5V (0x08) /* XT5V should always be reset */
#define DIVA0 (0x10) /* ACLK Divider 0 */
#define DIVA1 (0x20) /* ACLK Divider 1 */
#define XTS (0x40) /* LFXTCLK 0:Low Freq. / 1: High Freq. */
#define XT2OFF (0x80) /* Enable XT2CLK */
#define DIVA_0 (0x00) /* ACLK Divider 0: /1 */
#define DIVA_1 (0x10) /* ACLK Divider 1: /2 */
#define DIVA_2 (0x20) /* ACLK Divider 2: /4 */
#define DIVA_3 (0x30) /* ACLK Divider 3: /8 */
#define DCOR (0x01) /* Enable External Resistor : 1 */
#define DIVS0 (0x02) /* SMCLK Divider 0 */
#define DIVS1 (0x04) /* SMCLK Divider 1 */
#define SELS (0x08) /* SMCLK Source Select 0:DCOCLK / 1:XT2CLK/LFXTCLK */
#define DIVM0 (0x10) /* MCLK Divider 0 */
#define DIVM1 (0x20) /* MCLK Divider 1 */
#define SELM0 (0x40) /* MCLK Source Select 0 */
#define SELM1 (0x80) /* MCLK Source Select 1 */
#define DIVS_0 (0x00) /* SMCLK Divider 0: /1 */
#define DIVS_1 (0x02) /* SMCLK Divider 1: /2 */
#define DIVS_2 (0x04) /* SMCLK Divider 2: /4 */
#define DIVS_3 (0x06) /* SMCLK Divider 3: /8 */
#define DIVM_0 (0x00) /* MCLK Divider 0: /1 */
#define DIVM_1 (0x10) /* MCLK Divider 1: /2 */
#define DIVM_2 (0x20) /* MCLK Divider 2: /4 */
#define DIVM_3 (0x30) /* MCLK Divider 3: /8 */
#define SELM_0 (0x00) /* MCLK Source Select 0: DCOCLK */
#define SELM_1 (0x40) /* MCLK Source Select 1: DCOCLK */
#define SELM_2 (0x80) /* MCLK Source Select 2: XT2CLK/LFXTCLK */
#define SELM_3 (0xC0) /* MCLK Source Select 3: LFXTCLK */
/*************************************************************
* Flash Memory
*************************************************************/
#define FCTL1_ (0x0128) /* FLASH Control 1 */
DEFW( FCTL1 , FCTL1_)
#define FCTL2_ (0x012A) /* FLASH Control 2 */
DEFW( FCTL2 , FCTL2_)
#define FCTL3_ (0x012C) /* FLASH Control 3 */
DEFW( FCTL3 , FCTL3_)
#define FRKEY (0x9600) /* Flash key returned by read */
#define FWKEY (0xA500) /* Flash key for write */
#define FXKEY (0x3300) /* for use with XOR instruction */
#define ERASE (0x0002) /* Enable bit for Flash segment erase */
#define MERAS (0x0004) /* Enable bit for Flash mass erase */
#define WRT (0x0040) /* Enable bit for Flash write */
#define BLKWRT (0x0080) /* Enable bit for Flash segment write */
#define SEGWRT (0x0080) /* old definition */ /* Enable bit for Flash segment write */
#define FN0 (0x0001) /* Devide Flash clock by 1 to 64 using FN0 to FN5 according to: */
#define FN1 (0x0002) /* 32*FN5 + 16*FN4 + 8*FN3 + 4*FN2 + 2*FN1 + FN0 + 1 */
#define FN2 (0x0004)
#define FN3 (0x0008)
#define FN4 (0x0010)
#define FN5 (0x0020)
#define FSSEL0 (0x0040) /* Flash clock select 0 */ /* to distinguish from USART SSELx */
#define FSSEL1 (0x0080) /* Flash clock select 1 */
#define FSSEL_0 (0x0000) /* Flash clock select: 0 - ACLK */
#define FSSEL_1 (0x0040) /* Flash clock select: 1 - MCLK */
#define FSSEL_2 (0x0080) /* Flash clock select: 2 - SMCLK */
#define FSSEL_3 (0x00C0) /* Flash clock select: 3 - SMCLK */
#define BUSY (0x0001) /* Flash busy: 1 */
#define KEYV (0x0002) /* Flash Key violation flag */
#define ACCVIFG (0x0004) /* Flash Access violation flag */
#define WAIT (0x0008) /* Wait flag for segment write */
#define LOCK (0x0010) /* Lock bit: 1 - Flash is locked (read only) */
#define EMEX (0x0020) /* Flash Emergency Exit */
/************************************************************
* Comparator A
************************************************************/
#define CACTL1_ (0x0059) /* Comparator A Control 1 */
DEFC( CACTL1 , CACTL1_)
#define CACTL2_ (0x005A) /* Comparator A Control 2 */
DEFC( CACTL2 , CACTL2_)
#define CAPD_ (0x005B) /* Comparator A Port Disable */
DEFC( CAPD , CAPD_)
#define CAIFG (0x01) /* Comp. A Interrupt Flag */
#define CAIE (0x02) /* Comp. A Interrupt Enable */
#define CAIES (0x04) /* Comp. A Int. Edge Select: 0:rising / 1:falling */
#define CAON (0x08) /* Comp. A enable */
#define CAREF0 (0x10) /* Comp. A Internal Reference Select 0 */
#define CAREF1 (0x20) /* Comp. A Internal Reference Select 1 */
#define CARSEL (0x40) /* Comp. A Internal Reference Enable */
#define CAEX (0x80) /* Comp. A Exchange Inputs */
#define CAREF_0 (0x00) /* Comp. A Int. Ref. Select 0 : Off */
#define CAREF_1 (0x10) /* Comp. A Int. Ref. Select 1 : 0.25*Vcc */
#define CAREF_2 (0x20) /* Comp. A Int. Ref. Select 2 : 0.5*Vcc */
#define CAREF_3 (0x30) /* Comp. A Int. Ref. Select 3 : Vt*/
#define CAOUT (0x01) /* Comp. A Output */
#define CAF (0x02) /* Comp. A Enable Output Filter */
#define P2CA0 (0x04) /* Comp. A Connect External Signal to CA0 : 1 */
#define P2CA1 (0x08) /* Comp. A Connect External Signal to CA1 : 1 */
#define CACTL24 (0x10)
#define CACTL25 (0x20)
#define CACTL26 (0x40)
#define CACTL27 (0x80)
#define CAPD0 (0x01) /* Comp. A Disable Input Buffer of Port Register .0 */
#define CAPD1 (0x02) /* Comp. A Disable Input Buffer of Port Register .1 */
#define CAPD2 (0x04) /* Comp. A Disable Input Buffer of Port Register .2 */
#define CAPD3 (0x08) /* Comp. A Disable Input Buffer of Port Register .3 */
#define CAPD4 (0x10) /* Comp. A Disable Input Buffer of Port Register .4 */
#define CAPD5 (0x20) /* Comp. A Disable Input Buffer of Port Register .5 */
#define CAPD6 (0x40) /* Comp. A Disable Input Buffer of Port Register .6 */
#define CAPD7 (0x80) /* Comp. A Disable Input Buffer of Port Register .7 */
/************************************************************
* Interrupt Vectors (offset from 0xFFE0)
************************************************************/
#define PORT1_VECTOR (2 * 2) /* 0xFFE4 Port 1 */
#define PORT2_VECTOR (3 * 2) /* 0xFFE6 Port 2 */
#define USART0TX_VECTOR (6 * 2) /* 0xFFEC USART 0 Transmit */
#define USART0RX_VECTOR (7 * 2) /* 0xFFEE USART 0 Receive */
#define TIMERA1_VECTOR (8 * 2) /* 0xFFF0 Timer A CC1-2, TA */
#define TIMERA0_VECTOR (9 * 2) /* 0xFFF2 Timer A CC0 */
#define WDT_VECTOR (10 * 2) /* 0xFFF4 Watchdog Timer */
#define COMPARATORA_VECTOR (11 * 2) /* 0xFFF6 Comparator A */
#define NMI_VECTOR (14 * 2) /* 0xFFFC Non-maskable */
#define RESET_VECTOR (15 * 2) /* 0xFFFE Reset [Highest Priority] */
#define UART0TX_VECTOR USART0TX_VECTOR
#define UART0RX_VECTOR USART0RX_VECTOR
/************************************************************
* End of Module
************************************************************/
#pragma language=default
#endif /* #ifndef __msp430x12x */
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -