📄 msp430x43x.h
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#define CHAR (0x10)
#define LISTEN (0x08)
#define SYNC (0x04)
#define MM (0x02)
#define SWRST (0x01)
#define CKPH (0x80) /* UTCTL */
#define CKPL (0x40)
#define SSEL1 (0x20)
#define SSEL0 (0x10)
#define URXSE (0x08)
#define TXWAKE (0x04)
#define STC (0x02)
#define TXEPT (0x01)
#define FE (0x80) /* URCTL */
#define PE (0x40)
#define OE (0x20)
#define BRK (0x10)
#define URXEIE (0x08)
#define URXWIE (0x04)
#define RXWAKE (0x02)
#define RXERR (0x01)
/************************************************************
* USART 0
************************************************************/
#define U0CTL_ (0x0070) /* USART 0 Control */
DEFC( U0CTL , U0CTL_)
#define U0TCTL_ (0x0071) /* USART 0 Transmit Control */
DEFC( U0TCTL , U0TCTL_)
#define U0RCTL_ (0x0072) /* USART 0 Receive Control */
DEFC( U0RCTL , U0RCTL_)
#define U0MCTL_ (0x0073) /* USART 0 Modulation Control */
DEFC( U0MCTL , U0MCTL_)
#define U0BR0_ (0x0074) /* USART 0 Baud Rate 0 */
DEFC( U0BR0 , U0BR0_)
#define U0BR1_ (0x0075) /* USART 0 Baud Rate 1 */
DEFC( U0BR1 , U0BR1_)
#define U0RXBUF_ (0x0076) /* USART 0 Receive Buffer */
READ_ONLY DEFC( U0RXBUF , U0RXBUF_)
#define U0TXBUF_ (0x0077) /* USART 0 Transmit Buffer */
DEFC( U0TXBUF , U0TXBUF_)
/* Alternate register names */
#define UCTL0_ U0CTL_ /* USART 0 Control */
DEFC( UCTL0 , UCTL0_)
#define UTCTL0_ U0TCTL_ /* USART 0 Transmit Control */
DEFC( UTCTL0 , UTCTL0_)
#define URCTL0_ U0RCTL_ /* USART 0 Receive Control */
DEFC( URCTL0 , URCTL0_)
#define UMCTL0_ U0MCTL_ /* USART 0 Modulation Control */
DEFC( UMCTL0 , UMCTL0_)
#define UBR00_ U0BR0_ /* USART 0 Baud Rate 0 */
DEFC( UBR00 , UBR00_)
#define UBR10_ U0BR1_ /* USART 0 Baud Rate 1 */
DEFC( UBR10 , UBR10_)
#define RXBUF0_ U0RXBUF_ /* USART 0 Receive Buffer */
READ_ONLY DEFC( RXBUF0 , RXBUF0_)
#define TXBUF0_ U0TXBUF_ /* USART 0 Transmit Buffer */
DEFC( TXBUF0 , TXBUF0_)
#define UCTL_0_ U0CTL_ /* USART 0 Control */
DEFC( UCTL_0 , UCTL_0_)
#define UTCTL_0_ U0TCTL_ /* USART 0 Transmit Control */
DEFC( UTCTL_0 , UTCTL_0_)
#define URCTL_0_ U0RCTL_ /* USART 0 Receive Control */
DEFC( URCTL_0 , URCTL_0_)
#define UMCTL_0_ U0MCTL_ /* USART 0 Modulation Control */
DEFC( UMCTL_0 , UMCTL_0_)
#define UBR0_0_ U0BR0_ /* USART 0 Baud Rate 0 */
DEFC( UBR0_0 , UBR0_0_)
#define UBR1_0_ U0BR1_ /* USART 0 Baud Rate 1 */
DEFC( UBR1_0 , UBR1_0_)
#define RXBUF_0_ U0RXBUF_ /* USART 0 Receive Buffer */
READ_ONLY DEFC( RXBUF_0 , RXBUF_0_)
#define TXBUF_0_ U0TXBUF_ /* USART 0 Transmit Buffer */
DEFC( TXBUF_0 , TXBUF_0_)
/************************************************************
* Timer A
************************************************************/
#define TAIV_ (0x012E) /* Timer A Interrupt Vector Word */
READ_ONLY DEFW( TAIV , TAIV_)
#define TACTL_ (0x0160) /* Timer A Control */
DEFW( TACTL , TACTL_)
#define TACCTL0_ (0x0162) /* Timer A Capture/Compare Control 0 */
DEFW( TACCTL0 , TACCTL0_)
#define TACCTL1_ (0x0164) /* Timer A Capture/Compare Control 1 */
DEFW( TACCTL1 , TACCTL1_)
#define TACCTL2_ (0x0166) /* Timer A Capture/Compare Control 2 */
DEFW( TACCTL2 , TACCTL2_)
#define TAR_ (0x0170) /* Timer A */
DEFW( TAR , TAR_)
#define TACCR0_ (0x0172) /* Timer A Capture/Compare 0 */
DEFW( TACCR0 , TACCR0_)
#define TACCR1_ (0x0174) /* Timer A Capture/Compare 1 */
DEFW( TACCR1 , TACCR1_)
#define TACCR2_ (0x0176) /* Timer A Capture/Compare 2 */
DEFW( TACCR2 , TACCR2_)
/* Alternate register names */
#define CCTL0_ TACCTL0_ /* Timer A Capture/Compare Control 0 */
DEFW( CCTL0 , CCTL0_)
#define CCTL1_ TACCTL1_ /* Timer A Capture/Compare Control 1 */
DEFW( CCTL1 , CCTL1_)
#define CCTL2_ TACCTL2_ /* Timer A Capture/Compare Control 2 */
DEFW( CCTL2 , CCTL2_)
#define CCR0_ TACCR0_ /* Timer A Capture/Compare 0 */
DEFW( CCR0 , CCR0_)
#define CCR1_ TACCR1_ /* Timer A Capture/Compare 1 */
DEFW( CCR1 , CCR1_)
#define CCR2_ TACCR2_ /* Timer A Capture/Compare 2 */
DEFW( CCR2 , CCR2_)
#define TASSEL2 (0x0400) /* unused */ /* to distinguish from USART SSELx */
#define TASSEL1 (0x0200) /* Timer A clock source select 0 */
#define TASSEL0 (0x0100) /* Timer A clock source select 1 */
#define ID1 (0x0080) /* Timer A clock input devider 1 */
#define ID0 (0x0040) /* Timer A clock input devider 0 */
#define MC1 (0x0020) /* Timer A mode control 1 */
#define MC0 (0x0010) /* Timer A mode control 0 */
#define TACLR (0x0004) /* Timer A counter clear */
#define TAIE (0x0002) /* Timer A counter interrupt enable */
#define TAIFG (0x0001) /* Timer A counter interrupt flag */
#define MC_0 (0*0x10) /* Timer A mode control: 0 - Stop */
#define MC_1 (1*0x10) /* Timer A mode control: 1 - Up to CCR0 */
#define MC_2 (2*0x10) /* Timer A mode control: 2 - Continous up */
#define MC_3 (3*0x10) /* Timer A mode control: 3 - Up/Down */
#define ID_0 (0*0x40) /* Timer A input divider: 0 - /1 */
#define ID_1 (1*0x40) /* Timer A input divider: 1 - /2 */
#define ID_2 (2*0x40) /* Timer A input divider: 2 - /4 */
#define ID_3 (3*0x40) /* Timer A input divider: 3 - /8 */
#define TASSEL_0 (0*0x100) /* Timer A clock source select: 0 - TACLK */
#define TASSEL_1 (1*0x100) /* Timer A clock source select: 1 - ACLK */
#define TASSEL_2 (2*0x100) /* Timer A clock source select: 2 - SMCLK */
#define TASSEL_3 (3*0x100) /* Timer A clock source select: 3 - INCLK */
#define CM1 (0x8000) /* Capture mode 1 */
#define CM0 (0x4000) /* Capture mode 0 */
#define CCIS1 (0x2000) /* Capture input select 1 */
#define CCIS0 (0x1000) /* Capture input select 0 */
#define SCS (0x0800) /* Capture sychronize */
#define SCCI (0x0400) /* Latched capture signal (read) */
#define CAP (0x0100) /* Capture mode: 1 /Compare mode : 0 */
#define OUTMOD2 (0x0080) /* Output mode 2 */
#define OUTMOD1 (0x0040) /* Output mode 1 */
#define OUTMOD0 (0x0020) /* Output mode 0 */
#define CCIE (0x0010) /* Capture/compare interrupt enable */
#define CCI (0x0008) /* Capture input signal (read) */
#define OUT (0x0004) /* PWM Output signal if output mode 0 */
#define COV (0x0002) /* Capture/compare overflow flag */
#define CCIFG (0x0001) /* Capture/compare interrupt flag */
#define OUTMOD_0 (0*0x20) /* PWM output mode: 0 - output only */
#define OUTMOD_1 (1*0x20) /* PWM output mode: 1 - set */
#define OUTMOD_2 (2*0x20) /* PWM output mode: 2 - PWM toggle/reset */
#define OUTMOD_3 (3*0x20) /* PWM output mode: 3 - PWM set/reset */
#define OUTMOD_4 (4*0x20) /* PWM output mode: 4 - toggle */
#define OUTMOD_5 (5*0x20) /* PWM output mode: 5 - Reset */
#define OUTMOD_6 (6*0x20) /* PWM output mode: 6 - PWM toggle/set */
#define OUTMOD_7 (7*0x20) /* PWM output mode: 7 - PWM reset/set */
#define CCIS_0 (0*0x1000) /* Capture input select: 0 - CCIxA */
#define CCIS_1 (1*0x1000) /* Capture input select: 1 - CCIxB */
#define CCIS_2 (2*0x1000) /* Capture input select: 2 - GND */
#define CCIS_3 (3*0x1000) /* Capture input select: 3 - Vcc */
#define CM_0 (0*0x4000u) /* Capture mode: 0 - disabled */
#define CM_1 (1*0x4000u) /* Capture mode: 1 - pos. edge */
#define CM_2 (2*0x4000u) /* Capture mode: 1 - neg. edge */
#define CM_3 (3*0x4000u) /* Capture mode: 1 - both edges */
/************************************************************
* Timer B
************************************************************/
#define TBIV_ (0x011E) /* Timer B Interrupt Vector Word */
READ_ONLY DEFW( TBIV , TBIV_)
#define TBCTL_ (0x0180) /* Timer B Control */
DEFW( TBCTL , TBCTL_)
#define TBCCTL0_ (0x0182) /* Timer B Capture/Compare Control 0 */
DEFW( TBCCTL0 , TBCCTL0_)
#define TBCCTL1_ (0x0184) /* Timer B Capture/Compare Control 1 */
DEFW( TBCCTL1 , TBCCTL1_)
#define TBCCTL2_ (0x0186) /* Timer B Capture/Compare Control 2 */
DEFW( TBCCTL2 , TBCCTL2_)
#define TBR_ (0x0190) /* Timer B */
DEFW( TBR , TBR_)
#define TBCCR0_ (0x0192) /* Timer B Capture/Compare 0 */
DEFW( TBCCR0 , TBCCR0_)
#define TBCCR1_ (0x0194) /* Timer B Capture/Compare 1 */
DEFW( TBCCR1 , TBCCR1_)
#define TBCCR2_ (0x0196) /* Timer B Capture/Compare 2 */
DEFW( TBCCR2 , TBCCR2_)
#define SHR1 (0x4000) /* Timer B Compare latch load group 1 */
#define SHR0 (0x2000) /* Timer B Compare latch load group 0 */
#define TBCLGRP1 (0x4000) /* Timer B Compare latch load group 1 */
#define TBCLGRP0 (0x2000) /* Timer B Compare latch load group 0 */
#define CNTL1 (0x1000) /* Counter lenght 1 */
#define CNTL0 (0x0800) /* Counter lenght 0 */
#define TBSSEL2 (0x0400) /* unused */
#define TBSSEL1 (0x0200) /* Clock source 1 */
#define TBSSEL0 (0x0100) /* Clock source 0 */
#define TBCLR (0x0004) /* Timer B counter clear */
#define TBIE (0x0002) /* Timer B interrupt enable */
#define TBIFG (0x0001) /* Timer B interrupt flag */
#define TBSSEL_0 (0*0x0100) /* Clock Source: TBCLK */
#define TBSSEL_1 (1*0x0100) /* Clock Source: ACLK */
#define TBSSEL_2 (2*0x0100) /* Clock Source: SMCLK */
#define TBSSEL_3 (3*0x0100) /* Clock Source: INCLK */
#define CNTL_0 (0*0x0800) /* Counter lenght: 16 bit */
#define CNTL_1 (1*0x0800) /* Counter lenght: 12 bit */
#define CNTL_2 (2*0x0800) /* Counter lenght: 10 bit */
#define CNTL_3 (3*0x0800) /* Counter lenght: 8 bit */
#define SHR_0 (0*0x2000) /* Timer B Group: 0 - individually */
#define SHR_1 (1*0x2000) /* Timer B Group: 1 - 3 groups (1-2, 3-4, 5-6) */
#define SHR_2 (2*0x2000) /* Timer B Group: 2 - 2 groups (1-3, 4-6)*/
#define SHR_3 (3*0x2000) /* Timer B Group: 3 - 1 group (all) */
#define TBCLGRP_0 (0*0x2000) /* Timer B Group: 0 - individually */
#define TBCLGRP_1 (1*0x2000) /* Timer B Group: 1 - 3 groups (1-2, 3-4, 5-6) */
#define TBCLGRP_2 (2*0x2000) /* Timer B Group: 2 - 2 groups (1-3, 4-6)*/
#define TBCLGRP_3 (3*0x2000) /* Timer B Group: 3 - 1 group (all) */
/* Additional Timer B Control Register bits are defined in Timer A */
#define SLSHR1 (0x0400) /* Compare latch load source 1 */
#define SLSHR0 (0x0200) /* Compare latch load source 0 */
#define CLLD1 (0x0400) /* Compare latch load source 1 */
#define CLLD0 (0x0200) /* Compare latch load source 0 */
#define SLSHR_0 (0*0x0200) /* Compare latch load sourec : 0 - immediate */
#define SLSHR_1 (1*0x0200) /* Compare latch load sourec : 1 - TBR counts to 0 */
#define SLSHR_2 (2*0x0200) /* Compare latch load sourec : 2 - up/down */
#define SLSHR_3 (3*0x0200) /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */
#define CLLD_0 (0*0x0200) /* Compare latch load sourec : 0 - immediate */
#define CLLD_1 (1*0x0200) /* Compare latch load sourec : 1 - TBR counts to 0 */
#define CLLD_2 (2*0x0200) /* Compare latch load sourec : 2 - up/down */
#define CLLD_3 (3*0x0200) /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */
/*************************************************************
* Flash Memory
*************************************************************/
#define FCTL1_ (0x0128) /* FLASH Control 1 */
DEFW( FCTL1 , FCTL1_)
#define FCTL2_ (0x012A) /* FLASH Control 2 */
DEFW( FCTL2 , FCTL2_)
#define FCTL3_ (0x012C) /* FLASH Control 3 */
DEFW( FCTL3 , FCTL3_)
#define FRKEY (0x9600) /* Flash key returned by read */
#define FWKEY (0xA500) /* Flash key for write */
#define FXKEY (0x3300) /* for use with XOR instruction */
#define ERASE (0x0002) /* Enable bit for Flash segment erase */
#define MERAS (0x0004) /* Enable bit for Flash mass erase */
#define WRT (0x0040) /* Enable bit for Flash write */
#define BLKWRT (0x0080) /* Enable bit for Flash segment write */
#define SEGWRT (0x0080) /* old definition */ /* Enable bit for Flash segment write */
#define FN0 (0x0001) /* Devide Flash clock by 1 to 64 using FN0 to FN5 according to: */
#define FN1 (0x0002) /* 32*FN5 + 16*FN4 + 8*FN3 + 4*FN2 + 2*FN1 + FN0 + 1 */
#define FN2 (0x0004)
#define FN3 (0x0008)
#define FN4 (0x0010)
#define FN5 (0x0020)
#define FSSEL0 (0x0040) /* Flash clock select 0 */ /* to distinguish from USART SSELx */
#define FSSEL1 (0x0080) /* Flash clock select 1 */
#define FSSEL_0 (0x0000) /* Flash clock select: 0 - ACLK */
#define FSSEL_1 (0x0040) /* Flash clock select: 1 - MCLK */
#define FSSEL_2 (0x0080) /* Flash clock select: 2 - SMCLK */
#define FSSEL_3 (0x00C0) /* Flash clock select: 3 - SMCLK */
#define BUSY (0x0001) /* Flash busy: 1 */
#define KEYV (0x0002) /* Flash Key violation flag */
#define ACCVIFG (0x0004) /* Flash Access violation flag */
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