msp430x41x.h

单相复费率MSP430硬件时钟参考代码,MSP413设计方案

DEFC(    LCDM6             , LCDM6_)
#define LCDM7_              (0x0097)  /* LCD Memory 7 */
DEFC(    LCDM7             , LCDM7_)
#define LCDM8_              (0x0098)  /* LCD Memory 8 */
DEFC(    LCDM8             , LCDM8_)
#define LCDM9_              (0x0099)  /* LCD Memory 9 */
DEFC(    LCDM9             , LCDM9_)
#define LCDM10_             (0x009A)  /* LCD Memory 10 */
DEFC(    LCDM10            , LCDM10_)
#define LCDM11_             (0x009B)  /* LCD Memory 11 */
DEFC(    LCDM11            , LCDM11_)
#define LCDM12_             (0x009C)  /* LCD Memory 12 */
DEFC(    LCDM12            , LCDM12_)
#define LCDM13_             (0x009D)  /* LCD Memory 13 */
DEFC(    LCDM13            , LCDM13_)
#define LCDM14_             (0x009E)  /* LCD Memory 14 */
DEFC(    LCDM14            , LCDM14_)
#define LCDM15_             (0x009F)  /* LCD Memory 15 */
DEFC(    LCDM15            , LCDM15_)
#define LCDM16_             (0x00A0)  /* LCD Memory 16 */
DEFC(    LCDM16            , LCDM16_)
#define LCDM17_             (0x00A1)  /* LCD Memory 17 */
DEFC(    LCDM17            , LCDM17_)
#define LCDM18_             (0x00A2)  /* LCD Memory 18 */
DEFC(    LCDM18            , LCDM18_)
#define LCDM19_             (0x00A3)  /* LCD Memory 19 */
DEFC(    LCDM19            , LCDM19_)
#define LCDM20_             (0x00A4)  /* LCD Memory 20 */
DEFC(    LCDM20            , LCDM20_)

#define LCDMA_              (LCDM10_) /* LCD Memory A */
DEFC(    LCDMA             , LCDMA_)
#define LCDMB_              (LCDM11_) /* LCD Memory B */
DEFC(    LCDMB             , LCDMB_)
#define LCDMC_              (LCDM12_) /* LCD Memory C */
DEFC(    LCDMC             , LCDMC_)
#define LCDMD_              (LCDM13_) /* LCD Memory D */
DEFC(    LCDMD             , LCDMD_)
#define LCDME_              (LCDM14_) /* LCD Memory E */
DEFC(    LCDME             , LCDME_)
#define LCDMF_              (LCDM15_) /* LCD Memory F */
DEFC(    LCDMF             , LCDMF_)

/************************************************************
* Timer A
************************************************************/

#define TAIV_               (0x012E)  /* Timer A Interrupt Vector Word */
READ_ONLY DEFW( TAIV           , TAIV_)
#define TACTL_              (0x0160)  /* Timer A Control */
DEFW(    TACTL             , TACTL_)
#define TACCTL0_            (0x0162)  /* Timer A Capture/Compare Control 0 */
DEFW(    TACCTL0           , TACCTL0_)
#define TACCTL1_            (0x0164)  /* Timer A Capture/Compare Control 1 */
DEFW(    TACCTL1           , TACCTL1_)
#define TACCTL2_            (0x0166)  /* Timer A Capture/Compare Control 2 */
DEFW(    TACCTL2           , TACCTL2_)
#define TAR_                (0x0170)  /* Timer A */
DEFW(    TAR               , TAR_)
#define TACCR0_             (0x0172)  /* Timer A Capture/Compare 0 */
DEFW(    TACCR0            , TACCR0_)
#define TACCR1_             (0x0174)  /* Timer A Capture/Compare 1 */
DEFW(    TACCR1            , TACCR1_)
#define TACCR2_             (0x0176)  /* Timer A Capture/Compare 2 */
DEFW(    TACCR2            , TACCR2_)

/* Alternate register names */
#define CCTL0_              TACCTL0_    /* Timer A Capture/Compare Control 0 */
DEFW(    CCTL0 , CCTL0_)
#define CCTL1_              TACCTL1_    /* Timer A Capture/Compare Control 1 */
DEFW(    CCTL1 , CCTL1_)
#define CCTL2_              TACCTL2_    /* Timer A Capture/Compare Control 2 */
DEFW(    CCTL2 , CCTL2_)
#define CCR0_               TACCR0_     /* Timer A Capture/Compare 0 */
DEFW(    CCR0 , CCR0_)
#define CCR1_               TACCR1_     /* Timer A Capture/Compare 1 */
DEFW(    CCR1 , CCR1_)
#define CCR2_               TACCR2_     /* Timer A Capture/Compare 2 */
DEFW(    CCR2 , CCR2_)

#define TASSEL2             (0x0400)  /* unused */        /* to distinguish from USART SSELx */
#define TASSEL1             (0x0200)  /* Timer A clock source select 0 */
#define TASSEL0             (0x0100)  /* Timer A clock source select 1 */
#define ID1                 (0x0080)  /* Timer A clock input devider 1 */
#define ID0                 (0x0040)  /* Timer A clock input devider 0 */
#define MC1                 (0x0020)  /* Timer A mode control 1 */
#define MC0                 (0x0010)  /* Timer A mode control 0 */
#define TACLR               (0x0004)  /* Timer A counter clear */
#define TAIE                (0x0002)  /* Timer A counter interrupt enable */
#define TAIFG               (0x0001)  /* Timer A counter interrupt flag */

#define MC_0                (0*0x10)  /* Timer A mode control: 0 - Stop */
#define MC_1                (1*0x10)  /* Timer A mode control: 1 - Up to CCR0 */
#define MC_2                (2*0x10)  /* Timer A mode control: 2 - Continous up */
#define MC_3                (3*0x10)  /* Timer A mode control: 3 - Up/Down */
#define ID_0                (0*0x40)  /* Timer A input divider: 0 - /1 */
#define ID_1                (1*0x40)  /* Timer A input divider: 1 - /2 */
#define ID_2                (2*0x40)  /* Timer A input divider: 2 - /4 */
#define ID_3                (3*0x40)  /* Timer A input divider: 3 - /8 */
#define TASSEL_0            (0*0x100) /* Timer A clock source select: 0 - TACLK */
#define TASSEL_1            (1*0x100) /* Timer A clock source select: 1 - ACLK  */
#define TASSEL_2            (2*0x100) /* Timer A clock source select: 2 - SMCLK */
#define TASSEL_3            (3*0x100) /* Timer A clock source select: 3 - INCLK */

#define CM1                 (0x8000)  /* Capture mode 1 */
#define CM0                 (0x4000)  /* Capture mode 0 */
#define CCIS1               (0x2000)  /* Capture input select 1 */
#define CCIS0               (0x1000)  /* Capture input select 0 */
#define SCS                 (0x0800)  /* Capture sychronize */
#define SCCI                (0x0400)  /* Latched capture signal (read) */
#define CAP                 (0x0100)  /* Capture mode: 1 /Compare mode : 0 */
#define OUTMOD2             (0x0080)  /* Output mode 2 */
#define OUTMOD1             (0x0040)  /* Output mode 1 */
#define OUTMOD0             (0x0020)  /* Output mode 0 */
#define CCIE                (0x0010)  /* Capture/compare interrupt enable */
#define CCI                 (0x0008)  /* Capture input signal (read) */
#define OUT                 (0x0004)  /* PWM Output signal if output mode 0 */
#define COV                 (0x0002)  /* Capture/compare overflow flag */
#define CCIFG               (0x0001)  /* Capture/compare interrupt flag */

#define OUTMOD_0            (0*0x20)  /* PWM output mode: 0 - output only */
#define OUTMOD_1            (1*0x20)  /* PWM output mode: 1 - set */
#define OUTMOD_2            (2*0x20)  /* PWM output mode: 2 - PWM toggle/reset */
#define OUTMOD_3            (3*0x20)  /* PWM output mode: 3 - PWM set/reset */
#define OUTMOD_4            (4*0x20)  /* PWM output mode: 4 - toggle */
#define OUTMOD_5            (5*0x20)  /* PWM output mode: 5 - Reset */
#define OUTMOD_6            (6*0x20)  /* PWM output mode: 6 - PWM toggle/set */
#define OUTMOD_7            (7*0x20)  /* PWM output mode: 7 - PWM reset/set */
#define CCIS_0              (0*0x1000) /* Capture input select: 0 - CCIxA */
#define CCIS_1              (1*0x1000) /* Capture input select: 1 - CCIxB */
#define CCIS_2              (2*0x1000) /* Capture input select: 2 - GND */
#define CCIS_3              (3*0x1000) /* Capture input select: 3 - Vcc */
#define CM_0                (0*0x4000u) /* Capture mode: 0 - disabled */
#define CM_1                (1*0x4000u) /* Capture mode: 1 - pos. edge */
#define CM_2                (2*0x4000u) /* Capture mode: 1 - neg. edge */
#define CM_3                (3*0x4000u) /* Capture mode: 1 - both edges */

/*************************************************************
* Flash Memory
*************************************************************/

#define FCTL1_              (0x0128)  /* FLASH Control 1 */
DEFW(    FCTL1             , FCTL1_)
#define FCTL2_              (0x012A)  /* FLASH Control 2 */
DEFW(    FCTL2             , FCTL2_)
#define FCTL3_              (0x012C)  /* FLASH Control 3 */
DEFW(    FCTL3             , FCTL3_)

#define FRKEY               (0x9600)  /* Flash key returned by read */
#define FWKEY               (0xA500)  /* Flash key for write */
#define FXKEY               (0x3300)  /* for use with XOR instruction */

#define ERASE               (0x0002)  /* Enable bit for Flash segment erase */
#define MERAS               (0x0004)  /* Enable bit for Flash mass erase */
#define WRT                 (0x0040)  /* Enable bit for Flash write */
#define BLKWRT              (0x0080)  /* Enable bit for Flash segment write */
#define SEGWRT              (0x0080)  /* old definition */ /* Enable bit for Flash segment write */

#define FN0                 (0x0001)  /* Devide Flash clock by 1 to 64 using FN0 to FN5 according to: */
#define FN1                 (0x0002)  /*  32*FN5 + 16*FN4 + 8*FN3 + 4*FN2 + 2*FN1 + FN0 + 1 */
#define FN2                 (0x0004)
#define FN3                 (0x0008)
#define FN4                 (0x0010)
#define FN5                 (0x0020)
#define FSSEL0              (0x0040)  /* Flash clock select 0 */        /* to distinguish from USART SSELx */
#define FSSEL1              (0x0080)  /* Flash clock select 1 */

#define FSSEL_0             (0x0000)  /* Flash clock select: 0 - ACLK */
#define FSSEL_1             (0x0040)  /* Flash clock select: 1 - MCLK */
#define FSSEL_2             (0x0080)  /* Flash clock select: 2 - SMCLK */
#define FSSEL_3             (0x00C0)  /* Flash clock select: 3 - SMCLK */

#define BUSY                (0x0001)  /* Flash busy: 1 */
#define KEYV                (0x0002)  /* Flash Key violation flag */
#define ACCVIFG             (0x0004)  /* Flash Access violation flag */
#define WAIT                (0x0008)  /* Wait flag for segment write */
#define LOCK                (0x0010)  /* Lock bit: 1 - Flash is locked (read only) */
#define EMEX                (0x0020)  /* Flash Emergency Exit */

/************************************************************
* Comparator A
************************************************************/

#define CACTL1_             (0x0059)  /* Comparator A Control 1 */
DEFC(    CACTL1            , CACTL1_)
#define CACTL2_             (0x005A)  /* Comparator A Control 2 */
DEFC(    CACTL2            , CACTL2_)
#define CAPD_               (0x005B)  /* Comparator A Port Disable */
DEFC(    CAPD              , CAPD_)

#define CAIFG               (0x01)    /* Comp. A Interrupt Flag */
#define CAIE                (0x02)    /* Comp. A Interrupt Enable */
#define CAIES               (0x04)    /* Comp. A Int. Edge Select: 0:rising / 1:falling */
#define CAON                (0x08)    /* Comp. A enable */
#define CAREF0              (0x10)    /* Comp. A Internal Reference Select 0 */
#define CAREF1              (0x20)    /* Comp. A Internal Reference Select 1 */
#define CARSEL              (0x40)    /* Comp. A Internal Reference Enable */
#define CAEX                (0x80)    /* Comp. A Exchange Inputs */

#define CAREF_0             (0x00)    /* Comp. A Int. Ref. Select 0 : Off */
#define CAREF_1             (0x10)    /* Comp. A Int. Ref. Select 1 : 0.25*Vcc */
#define CAREF_2             (0x20)    /* Comp. A Int. Ref. Select 2 : 0.5*Vcc */
#define CAREF_3             (0x30)    /* Comp. A Int. Ref. Select 3 : Vt*/

#define CAOUT               (0x01)    /* Comp. A Output */
#define CAF                 (0x02)    /* Comp. A Enable Output Filter */
#define P2CA0               (0x04)    /* Comp. A Connect External Signal to CA0 : 1 */
#define P2CA1               (0x08)    /* Comp. A Connect External Signal to CA1 : 1 */
#define CACTL24             (0x10)
#define CACTL25             (0x20)
#define CACTL26             (0x40)
#define CACTL27             (0x80)

#define CAPD0               (0x01)    /* Comp. A Disable Input Buffer of Port Register .0 */
#define CAPD1               (0x02)    /* Comp. A Disable Input Buffer of Port Register .1 */
#define CAPD2               (0x04)    /* Comp. A Disable Input Buffer of Port Register .2 */
#define CAPD3               (0x08)    /* Comp. A Disable Input Buffer of Port Register .3 */
#define CAPD4               (0x10)    /* Comp. A Disable Input Buffer of Port Register .4 */
#define CAPD5               (0x20)    /* Comp. A Disable Input Buffer of Port Register .5 */
#define CAPD6               (0x40)    /* Comp. A Disable Input Buffer of Port Register .6 */
#define CAPD7               (0x80)    /* Comp. A Disable Input Buffer of Port Register .7 */

/************************************************************
* Interrupt Vectors (offset from 0xFFE0)
************************************************************/

#define BASICTIMER_VECTOR   (0 * 2)  /* 0xFFE0 Basic Timer */
#define PORT2_VECTOR        (1 * 2)  /* 0xFFE2 Port 2 */
#define PORT1_VECTOR        (4 * 2)  /* 0xFFE8 Port 1 */
#define TIMERA1_VECTOR      (5 * 2)  /* 0xFFEA Timer A CC1-2, TA */
#define TIMERA0_VECTOR      (6 * 2)  /* 0xFFEC Timer A CC0 */
#define WDT_VECTOR          (10 * 2) /* 0xFFF4 Watchdog Timer */
#define COMPARATORA_VECTOR  (11 * 2) /* 0xFFF6 Comparator A */
#define NMI_VECTOR          (14 * 2) /* 0xFFFC Non-maskable */
#define RESET_VECTOR        (15 * 2) /* 0xFFFE Reset [Highest Priority] */

/************************************************************
* End of Module
************************************************************/

#pragma language=default

#endif /* #ifndef __msp430x41x */