📄 msp430x41x.h
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READ_ONLY DEFC( P5IN , P5IN_)
#define P5OUT_ (0x0031) /* Port 5 Output */
DEFC( P5OUT , P5OUT_)
#define P5DIR_ (0x0032) /* Port 5 Direction */
DEFC( P5DIR , P5DIR_)
#define P5SEL_ (0x0033) /* Port 5 Selection */
DEFC( P5SEL , P5SEL_)
#define P6IN_ (0x0034) /* Port 6 Input */
READ_ONLY DEFC( P6IN , P6IN_)
#define P6OUT_ (0x0035) /* Port 6 Output */
DEFC( P6OUT , P6OUT_)
#define P6DIR_ (0x0036) /* Port 6 Direction */
DEFC( P6DIR , P6DIR_)
#define P6SEL_ (0x0037) /* Port 6 Selection */
DEFC( P6SEL , P6SEL_)
/************************************************************
* BASIC TIMER
************************************************************/
#define BTCTL_ (0x0040) /* Basic Timer Control */
DEFC( BTCTL , BTCTL_)
/* The bit names have been prefixed with "BT" */
#define BTIP0 (0x01)
#define BTIP1 (0x02)
#define BTIP2 (0x04)
#define BTFRFQ0 (0x08)
#define BTFRFQ1 (0x10)
#define BTDIV (0x20) /* fCLK2 , ACLK:256 */
/*#define BTRESET (0x40)*/ /* incorrect :BT is reset and BTIFG is reset if this bit is set */
#define BTHOLD (0x40) /* BT1 is held if this bit is set */
#define BTSSEL (0x80) /* fBT , fMCLK (main clock) */
#define BTCNT1_ (0x0046) /* Basic Timer Count 1 */
DEFC( BTCNT1 , BTCNT1_)
#define BTCNT2_ (0x0047) /* Basic Timer Count 2 */
DEFC( BTCNT2 , BTCNT2_)
/* Frequency of the BTCNT2 coded with Bit 5 and 7 in BTCTL */
#define BT_fCLK2_ACLK (0x00)
#define BT_fCLK2_ACLK_DIV256 (BTDIV)
#define BT_fCLK2_MCLK (BTSSEL)
/* Interrupt interval time fINT coded with Bits 0-2 in BTCTL */
#define BT_fCLK2_DIV2 (0x00) /* fINT , fCLK2:2 (default) */
#define BT_fCLK2_DIV4 (BTIP0) /* fINT , fCLK2:4 */
#define BT_fCLK2_DIV8 (BTIP1) /* fINT , fCLK2:8 */
#define BT_fCLK2_DIV16 (BTIP1+BTIP0) /* fINT , fCLK2:16 */
#define BT_fCLK2_DIV32 (BTIP2) /* fINT , fCLK2:32 */
#define BT_fCLK2_DIV64 (BTIP2+BTIP0) /* fINT , fCLK2:64 */
#define BT_fCLK2_DIV128 (BTIP2+BTIP1) /* fINT , fCLK2:128 */
#define BT_fCLK2_DIV256 (BTIP2+BTIP1+BTIP0) /* fINT , fCLK2:256 */
/* Frequency of LCD coded with Bits 3-4 */
#define BT_fLCD_DIV32 (0x00) /* fLCD , fACLK:32 (default) */
#define BT_fLCD_DIV64 (BTFRFQ0) /* fLCD , fACLK:64 */
#define BT_fLCD_DIV128 (BTFRFQ1) /* fLCD , fACLK:128 */
#define BT_fLCD_DIV256 (BTFRFQ1+BTFRFQ0) /* fLCD , fACLK:256 */
/* LCD frequency values with fBT,fACLK */
#define BT_fLCD_1K (0x00) /* fACLK:32 (default) */
#define BT_fLCD_512 (BTFRFQ0) /* fACLK:64 */
#define BT_fLCD_256 (BTFRFQ1) /* fACLK:128 */
#define BT_fLCD_128 (BTFRFQ1+BTFRFQ0) /* fACLK:256 */
/* LCD frequency values with fBT,fMCLK */
#define BT_fLCD_31K (BTSSEL) /* fMCLK:32 */
#define BT_fLCD_15_5K (BTSSEL+BTFRFQ0) /* fMCLK:64 */
#define BT_fLCD_7_8K (BTSSEL+BTFRFQ1+BTFRFQ0) /* fMCLK:256 */
/* with assumed vlues of fACLK,32KHz, fMCLK,1MHz */
/* fBT,fACLK is thought for longer interval times */
#define BT_ADLY_0_064 (0x00) /* 0.064ms interval (default) */
#define BT_ADLY_0_125 (BTIP0) /* 0.125ms " */
#define BT_ADLY_0_25 (BTIP1) /* 0.25ms " */
#define BT_ADLY_0_5 (BTIP1+BTIP0) /* 0.5ms " */
#define BT_ADLY_1 (BTIP2) /* 1ms " */
#define BT_ADLY_2 (BTIP2+BTIP0) /* 2ms " */
#define BT_ADLY_4 (BTIP2+BTIP1) /* 4ms " */
#define BT_ADLY_8 (BTIP2+BTIP1+BTIP0) /* 8ms " */
#define BT_ADLY_16 (BTDIV) /* 16ms " */
#define BT_ADLY_32 (BTDIV+BTIP0) /* 32ms " */
#define BT_ADLY_64 (BTDIV+BTIP1) /* 64ms " */
#define BT_ADLY_125 (BTDIV+BTIP1+BTIP0) /* 125ms " */
#define BT_ADLY_250 (BTDIV+BTIP2) /* 250ms " */
#define BT_ADLY_500 (BTDIV+BTIP2+BTIP0) /* 500ms " */
#define BT_ADLY_1000 (BTDIV+BTIP2+BTIP1) /* 1000ms " */
#define BT_ADLY_2000 (BTDIV+BTIP2+BTIP1+BTIP0) /* 2000ms " */
/* fCLK2,fMCLK (1MHz) is thought for short interval times */
/* the timing for short intervals is more precise than ACLK */
/* NOTE */
/* Be sure that the SCFQCTL-Register is set to 01Fh so that fMCLK,1MHz */
/* Too low interval time results in interrupts too frequent for the processor to handle! */
#define BT_MDLY_0_002 (BTSSEL) /* 0.002ms interval *** interval times */
#define BT_MDLY_0_004 (BTSSEL+BTIP0) /* 0.004ms " *** too short for */
#define BT_MDLY_0_008 (BTSSEL+BTIP1) /* 0.008ms " *** interrupt */
#define BT_MDLY_0_016 (BTSSEL+BTIP1+BTIP0) /* 0.016ms " *** handling */
#define BT_MDLY_0_032 (BTSSEL+BTIP2) /* 0.032ms " */
#define BT_MDLY_0_064 (BTSSEL+BTIP2+BTIP0) /* 0.064ms " */
#define BT_MDLY_0_125 (BTSSEL+BTIP2+BTIP1) /* 0.125ms " */
#define BT_MDLY_0_25 (BTSSEL+BTIP2+BTIP1+BTIP0)/* 0.25ms " */
/* Reset/Hold coded with Bits 6-7 in BT(1)CTL */
/* this is for BT */
#define BTRESET_CNT1 (BTRESET) /* BTCNT1 is reset while BTRESET is set */
#define BTRESET_CNT1_2 (BTRESET+BTDIV) /* BTCNT1 .AND. BTCNT2 are reset while ~ is set */
/* this is for BT1 */
#define BTHOLD_CNT1 (BTHOLD) /* BTCNT1 is held while BTHOLD is set */
#define BTHOLD_CNT1_2 (BTHOLD+BTDIV) /* BT1CNT1 .AND. BT1CNT2 are held while ~ is set */
/* INTERRUPT CONTROL BITS */
/* #define BTIE 0x80 */
/* #define BTIFG 0x80 */
/************************************************************
* SYSTEM CLOCK, FLL+ (x41x)
************************************************************/
#define SCFI0_ (0x0050) /* System Clock Frequency Integrator 0 */
DEFC( SCFI0 , SCFI0_)
#define FN_2 (0x04) /* fDCOCLK , 2*fNominal */
#define FN_3 (0x08) /* fDCOCLK , 3*fNominal */
#define FN_4 (0x10) /* fDCOCLK , 4.5*fNominal */
#define FN_8 (0x20) /* fDCOCLK , 10*fNominal */
#define FLLD0 (0x40) /* Loop Divider Bit : 0 */
#define FLLD1 (0x80) /* Loop Divider Bit : 1 */
#define FLLD_1 (0x00) /* Multiply Selected Loop Freq. By 1 */
#define FLLD_2 (0x40) /* Multiply Selected Loop Freq. By 2 */
#define FLLD_4 (0x80) /* Multiply Selected Loop Freq. By 4 */
#define FLLD_8 (0xC0) /* Multiply Selected Loop Freq. By 8 */
#define SCFI1_ (0x0051) /* System Clock Frequency Integrator 1 */
DEFC( SCFI1 , SCFI1_)
#define SCFQCTL_ (0x0052) /* System Clock Frequency Control */
DEFC( SCFQCTL , SCFQCTL_)
/* System clock frequency values fMCLK coded with Bits 0-6 in SCFQCTL */
/* #define SCFQ_32K 0x00 fMCLK,1*fACLK only a range from */
#define SCFQ_64K (0x01) /* fMCLK,2*fACLK 1+1 to 127+1 is possible */
#define SCFQ_128K (0x03) /* fMCLK,4*fACLK */
#define SCFQ_256K (0x07) /* fMCLK,8*fACLK */
#define SCFQ_512K (0x0F) /* fMCLK,16*fACLK */
#define SCFQ_1M (0x1F) /* fMCLK,32*fACLK */
#define SCFQ_2M (0x3F) /* fMCLK,64*fACLK */
#define SCFQ_4M (0x7F) /* fMCLK,128*fACLK */
#define SCFQ_M (0x80) /* Modulation Disable */
#define FLL_CTL0_ (0x0053) /* FLL+ Control 0 */
DEFC( FLL_CTL0 , FLL_CTL0_)
#define DCOF (0x01) /* DCO Fault Flag */
#define LFOF (0x02) /* Low Frequency Oscillator Fault Flag */
#define XT1OF (0x04) /* High Frequency Oscillator Fault Flag */
#define OSCCAP0 (0x10) /* XIN/XOUT Cap 0 */
#define OSCCAP1 (0x20) /* XIN/XOUT Cap 1 */
#define XTS_FLL (0x40) /* 1: Selects high-freq. oscillator */
#define DCOPLUS (0x80) /* DCO+ Enable */
#define XCAP0PF (0x00) /* XIN Cap = XOUT Cap = 0pf */
#define XCAP10PF (0x10) /* XIN Cap = XOUT Cap = 10pf */
#define XCAP14PF (0x20) /* XIN Cap = XOUT Cap = 14pf */
#define XCAP18PF (0x30) /* XIN Cap = XOUT Cap = 18pf */
#define FLL_CTL1_ (0x0054) /* FLL+ Control 1 */
DEFC( FLL_CTL1 , FLL_CTL1_)
#define FLL_DIV0 (0x00) /* FLL+ Divide Px.x/ACLK 0 */
#define FLL_DIV1 (0x01) /* FLL+ Divide Px.x/ACLK 1 */
#define FLL_DIV_1 (0x00) /* FLL+ Divide Px.x/ACLK By 1 */
#define FLL_DIV_2 (0x01) /* FLL+ Divide Px.x/ACLK By 2 */
#define FLL_DIV_4 (0x02) /* FLL+ Divide Px.x/ACLK By 4 */
#define FLL_DIV_8 (0x03) /* FLL+ Divide Px.x/ACLK By 8 */
/* INTERRUPT CONTROL BITS */
/* These two bits are defined in the Special Function Registers */
/* #define OFIFG 0x02 */
/* #define OFIE 0x02 */
/************************************************************
* Brown-Out, Supply Voltage Supervision (SVS)
************************************************************/
#define SVSCTL_ (0x0056) /* SVS Control */
DEFC( SVSCTL , SVSCTL_)
#define SVSFG (0x01)
#define SVSOP (0x02)
#define SVSON (0x04)
#define PORON (0x08)
#define VLDOFF (0x00)
#define VLDON (0x10)
#define VLD_1_8V (0x10)
/************************************************************
* LCD
************************************************************/
#define LCDCTL_ (0x0090) /* LCD Control */
DEFC( LCDCTL , LCDCTL_)
/* the names of the mode bits are different from the spec */
#define LCDON (0x01)
#define LCDLOWR (0x02)
#define LCDSON (0x04)
#define LCDMX0 (0x08)
#define LCDMX1 (0x10)
#define LCDP0 (0x20)
#define LCDP1 (0x40)
#define LCDP2 (0x80)
/* Display modes coded with Bits 2-4 */
#define LCDSTATIC (LCDSON)
#define LCD2MUX (LCDMX0+LCDSON)
#define LCD3MUX (LCDMX1+LCDSON)
#define LCD4MUX (LCDMX1+LCDMX0+LCDSON)
/* Group select code with Bits 5-7 Seg.lines Dig.output */
#define LCDSG0 (0x00) /* --------- Port Only (default) */
#define LCDSG0_1 (LCDP0) /* S0 - S15 see Datasheet */
#define LCDSG0_2 (LCDP1) /* S0 - S19 see Datasheet */
#define LCDSG0_3 (LCDP1+LCDP0) /* S0 - S23 see Datasheet */
#define LCDSG0_4 (LCDP2) /* S0 - S27 see Datasheet */
#define LCDSG0_5 (LCDP2+LCDP0) /* S0 - S31 see Datasheet */
#define LCDSG0_6 (LCDP2+LCDP1) /* S0 - S35 see Datasheet */
#define LCDSG0_7 (LCDP2+LCDP1+LCDP0) /* S0 - S39 see Datasheet */
/* NOTE: YOU CAN ONLY USE THE 'S' OR 'G' DECLARATIONS FOR A COMMAND */
/* MOV #LCDSG0_3+LCDOG2_7,&LCDCTL ACTUALY MEANS MOV #LCDP1,&LCDCTL! */
#define LCDOG1_7 (0x00) /* --------- Port Only (default) */
#define LCDOG2_7 (LCDP0) /* S0 - S15 see Datasheet */
#define LCDOG3_7 (LCDP1) /* S0 - S19 see Datasheet */
#define LCDOG4_7 (LCDP1+LCDP0) /* S0 - S23 see Datasheet */
#define LCDOG5_7 (LCDP2) /* S0 - S27 see Datasheet */
#define LCDOG6_7 (LCDP2+LCDP0) /* S0 - S31 see Datasheet */
#define LCDOG7 (LCDP2+LCDP1) /* S0 - S35 see Datasheet */
#define LCDOGOFF (LCDP2+LCDP1+LCDP0) /* S0 - S39 see Datasheet */
#define LCDMEM_ (0x0091) /* LCD Memory */
#ifndef __IAR_SYSTEMS_ICC
#define LCDMEM (LCDMEM_) /* LCD Memory (for assembler) */
#else
#define LCDMEM ((char*) LCDMEM_) /* LCD Memory (for C) */
#endif
#define LCDM1_ (LCDMEM_) /* LCD Memory 1 */
DEFC( LCDM1 , LCDM1_)
#define LCDM2_ (0x0092) /* LCD Memory 2 */
DEFC( LCDM2 , LCDM2_)
#define LCDM3_ (0x0093) /* LCD Memory 3 */
DEFC( LCDM3 , LCDM3_)
#define LCDM4_ (0x0094) /* LCD Memory 4 */
DEFC( LCDM4 , LCDM4_)
#define LCDM5_ (0x0095) /* LCD Memory 5 */
DEFC( LCDM5 , LCDM5_)
#define LCDM6_ (0x0096) /* LCD Memory 6 */
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