📄 app_sender.c
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};*//*struct __nesc_attr_atleastonce {};*//*struct __nesc_attr_exactlyonce {};*/enum __nesc_unnamed4252 { SUCCESS = 0, FAIL = 1, ESIZE = 2, ECANCEL = 3, EOFF = 4, EBUSY = 5, EINVAL = 6, ERETRY = 7, ERESERVE = 8, EALREADY = 9};typedef uint8_t error_t ;static /*inline*/ error_t ecombine(error_t r1, error_t r2);sbit EA = 0xAF;sbit P1_0 = 0x90;sbit P1_1 = 0x91;enum __nesc_unnamed4253 { CC2430_IEN0_EA = 0x7, CC2430_IEN0_STIE = 0x5, CC2430_IEN0_ENCIE = 0x4, CC2430_IEN0_URX1IE = 0x3, CC2430_IEN0_URX0IE = 0x2, CC2430_IEN0_ADCIE = 0x1, CC2430_IEN0_RFERRIE = 0x0};enum __nesc_unnamed4254 { CC2430_IEN2_WDTIE = 0x5, CC2430_IEN2_P1IE = 0x4, CC2430_IEN2_UTX1IE = 0x3, CC2430_IEN2_UTX0IE = 0x2, CC2430_IEN2_P2IE = 0x1, CC2430_IEN2_RFIE = 0x0};enum __nesc_unnamed4255 { CC2430_IRCON_STIF = 0x7, CC2430_IRCON_P0IF = 0x5, CC2430_IRCON_T4IF = 0x4, CC2430_IRCON_T3IF = 0x3, CC2430_IRCON_T2IF = 0x2, CC2430_IRCON_T1IF = 0x1, CC2430_IRCON_DMAIF = 0x0};enum __nesc_unnamed4256 { CC2430_IRCON2_WDTIF = 0x4, CC2430_IRCON2_P1IF = 0x3, CC2430_IRCON2_UTX1IF = 0x2, CC2430_IRCON2_UTX0IF = 0x1, CC2430_IRCON2_P2IF = 0x0};enum __nesc_unnamed4257 { CC2430_RFIM_RREG_PD = 0x7, CC2430_RFIM_TXDONE = 0x6, CC2430_RFIM_FIFOP = 0x5, CC2430_RFIM_SFD = 0x4, CC2430_RFIM_CCA = 0x3, CC2430_RFIM_CSP_WT = 0x2, CC2430_RFIM_CSP_STOP = 0x1, CC2430_RFIM_CSP_INT = 0x0};enum __nesc_unnamed4258 { CC2430_RFIF_RREG_ON = 0x7, CC2430_RFIF_TXDONE = 0x6, CC2430_RFIF_FIFOP = 0x5, CC2430_RFIF_SFD = 0x4, CC2430_RFIF_CCA = 0x3, CC2430_RFIF_CSP_WT = 0x2, CC2430_RFIF_CSP_STOP = 0x1, CC2430_RFIF_CSP_INT = 0x0};sfr U0CSR = 0x86;sbit URX0IF = 0x8B;sbit RFERRIF = 0x89;sfr RFIM = 0x91;sfr IEN2 = 0x9A;sfr S1CON = 0x9B;sbit RFERRIE = 0xA8;sbit URX0IE = 0xAA;sbit T1IE = 0xB9;sfr SLEEP = 0xBE;sfr U0BUF = 0xC1;sfr U0BAUD = 0xC2;sfr U0UCR = 0xC4;sfr U0GCR = 0xC5;sfr CLKCON = 0xC6;sfr TIMIF = 0xD8;sfr RFD = 0xD9;sfr T1CC0L = 0xDA;sfr T1CC0H = 0xDB;sfr RFST = 0xE1;sfr T1CNTL = 0xE2;sfr T1CNTH = 0xE3;sfr T1CTL = 0xE4;sfr T1CCTL0 = 0xE5;sfr T1CCTL1 = 0xE6;sfr T1CCTL2 = 0xE7;sbit UTX0IF = 0xE9;sfr RFIF = 0xE9;sfr PERCFG = 0xF1;sfr P1_DIR = 0xFE;sfr P0_ALT = 0xF3;//typedef uint16_t uint16_t xdata;//typedef uint8_t uint8_t xdata;//typedef uint16_t uint16_t code;//typedef uint8_t uint8_t code;enum __nesc_unnamed4259 { CC2430_RFPWR_ADI_RADIO_PD = 0x4, CC2430_RFPWR_RREG_RADIO_PD = 0x3, CC2430_RFPWR_RREG_DELAY = 0x0, CC2430_RFPWR_RREG_DELAY_MASK = 0x7};enum __nesc_unnamed4260 { CC2430_RREG_DELAY_0 = 0x0, CC2430_RREG_DELAY_31 = 0x1, CC2430_RREG_DELAY_63 = 0x2, CC2430_RREG_DELAY_125 = 0x3, CC2430_RREG_DELAY_250 = 0x4, CC2430_RREG_DELAY_500 = 0x5, CC2430_RREG_DELAY_1000 = 0x6, CC2430_RREG_DELAY_2000 = 0x7};enum __nesc_unnamed4261 { CC2430_MDMCTRL0L_AUTOCRC = 0x5, CC2430_MDMCTRL0L_AUTOACK = 0x4};enum __nesc_unnamed4262 { CC2430_MDMCTRL0H_FRAME_FILT = 0x6, CC2430_MDMCTRL0H_RESERVED_FRAME_MODE = 0x5, CC2430_MDMCTRL0H_PAN_COORDINATOR = 0x4, CC2430_MDMCTRL0H_ADDR_DECODE = 0x3, CC2430_MDMCTRL0H_CCA_HYST = 0x0};enum __nesc_unnamed4263 { CC2430_RFSTATUS_TX_ACTIVE = 0x4, CC2430_RFSTATUS_FIFO = 0x3, CC2430_RFSTATUS_FIFOP = 0x2, CC2430_RFSTATUS_SFD = 0x1, CC2430_RFSTATUS_CCA = 0x0};typedef uint8_t __nesc_atomic_t;static /*inline*/ void __nesc_disable_interrupt(void);static /*inline*/ void __nesc_enable_interrupt(void); /*inline*/ __nesc_atomic_t __nesc_atomic_start(void ) ; /*inline*/ void __nesc_atomic_end(__nesc_atomic_t oldSreg) ;enum __nesc_unnamed4264 { CC2430_SLEEP_OSC32K_CALDIS = 7, CC2430_SLEEP_XOSC_STB = 6, CC2430_SLEEP_HFRC_STB = 5, CC2430_SLEEP_DIV = 3, CC2430_SLEEP_OSC_PD = 2, CC2430_SLEEP_MODE = 0, CC2430_SLEEP_MODE_MASK = 3};enum __nesc_unnamed4265 { CC2430_SLEEP_POWERMODE_0 = 0, CC2430_SLEEP_POWERMODE_1 = 1, CC2430_SLEEP_POWERMODE_2 = 2, CC2430_SLEEP_POWERMODE_3 = 3};enum __nesc_unnamed4266 { CC2430_CLKCON_OSC32K = 7, CC2430_CLKCON_OSC = 6, CC2430_CLKCON_TICKSPD = 3, CC2430_CLKCON_CLKSPD = 0, CC2430_CLKCON_TICKSPD_MASK = 0x38};enum cc2430_tick_spd_t { CC2430_TICKF_DIV_1 = 0x0 << CC2430_CLKCON_TICKSPD, CC2430_TICKF_DIV_2 = 0x1 << CC2430_CLKCON_TICKSPD, CC2430_TICKF_DIV_4 = 0x2 << CC2430_CLKCON_TICKSPD, CC2430_TICKF_DIV_8 = 0x3 << CC2430_CLKCON_TICKSPD, CC2430_TICKF_DIV_16 = 0x4 << CC2430_CLKCON_TICKSPD, CC2430_TICKF_DIV_32 = 0x5 << CC2430_CLKCON_TICKSPD, CC2430_TICKF_DIV_64 = 0x6 << CC2430_CLKCON_TICKSPD, CC2430_TICKF_DIV_128 = 0x7 << CC2430_CLKCON_TICKSPD};enum __nesc_unnamed4267 { CC2430_T1CTL_CH2IF = 0x7, CC2430_T1CTL_CH1IF = 0x6, CC2430_T1CTL_CH0IF = 0x5, CC2430_T1CTL_OVFIF = 0x4, CC2430_T1CTL_DIV = 0x2, CC2430_T1CTL_MODE = 0x0, CC2430_T1CTL_MODE_MASK = 0x3, CC2430_T1CTL_DIV_MASK = 0xc, CC2430_T1CTL_IF_MASK = 0xf0};enum cc2430_timer1_mode_t { CC2430_TIMER1_MODE_OFF = 0x0 << CC2430_T1CTL_MODE, CC2430_TIMER1_MODE_FREE = 0x1 << CC2430_T1CTL_MODE, CC2430_TIMER1_MODE_MODULO = 0x2 << CC2430_T1CTL_MODE, CC2430_TIMER1_MODE_UPDOWN = 0x3 << CC2430_T1CTL_MODE};enum cc2430_timer1_if_t { CC2430_T1_CH2IF = 1 << CC2430_T1CTL_CH2IF, CC2430_T1_CH1IF = 1 << CC2430_T1CTL_CH1IF, CC2430_T1_CH0IF = 1 << CC2430_T1CTL_CH0IF, CC2430_T1_OVFIF = 1 << CC2430_T1CTL_OVFIF};enum cc2430_timer1_prescaler_t { CC2430_TIMER1_DIV_1 = 0x0 << CC2430_T1CTL_DIV, CC2430_TIMER1_DIV_8 = 0x1 << CC2430_T1CTL_DIV, CC2430_TIMER1_DIV_32 = 0x2 << CC2430_T1CTL_DIV, CC2430_TIMER1_DIV_128 = 0x3 << CC2430_T1CTL_DIV};enum __nesc_unnamed4268 { CC2430_T1CCTLx_CPSEL = 0x7, CC2430_T1CCTLx_IM = 0x6, CC2430_T1CCTLx_CMP = 0x3, CC2430_T1CCTLx_MODE = 0x2, CC2430_T1CCTLx_CAP = 0x0};enum cc2430_timerMAC_mode_t { CC2430_TIMERMAC_MODE_IDLE = 0x0, CC2430_TIMERMAC_MODE_RUN = 0x1};enum cc2430_timerMAC_T2CNF_t { CC2430_T2CNF_CMPIF = 0x7, CC2430_T2CNF_PERIF = 0x6, CC2430_T2CNF_OFCMPIF = 0x5, CC2430_T2CNF_CMSEL = 0x3, CC2430_T2CNF_SYNC = 0x1, CC2430_T2CNF_RUN = 0x0};enum cc2430_timerMAC_T2PEROF2_t { CC2430_T2PEROF2_CMPIM = 0x7, CC2430_T2PEROF2_PERIM = 0x6, CC2430_T2PEROF2_OFCMPIM = 0x5};enum cc2430_timerMAC_if_t { CC2430_TMAC_CMPIF = 1 << CC2430_T2CNF_CMPIF, CC2430_TMAC_PERIF = 1 << CC2430_T2CNF_PERIF, CC2430_TMAC_OFCMPIF = 1 << CC2430_T2CNF_OFCMPIF};enum cc2430_timerMAC_interval_t { CC2430_TIMERWDT_32768 = 0, CC2430_TIMERWDT_8192 = 1, CC2430_TIMERWDT_512 = 2, CC2430_TIMERWDT_64 = 3};enum __nesc_unnamed4269 { CC2430_TIMIF_OVFIM = 0x6};enum cc2430_timer34_if_t { CC2430_TIMIF_T4CH1IF = 0x5, CC2430_TIMIF_T4CH0IF = 0x4, CC2430_TIMIF_T4OVFIF = 0x3, CC2430_TIMIF_T3CH1IF = 0x2, CC2430_TIMIF_T3CH0IF = 0x1, CC2430_TIMIF_T3OVFIF = 0x0};enum cc2430_timer3_4_mode_t { CC2430_TIMER3_4_MODE_FREE = 0x0, CC2430_TIMER3_4_MODE_DOWN = 0x1, CC2430_TIMER3_4_MODE_MODULO = 0x2, CC2430_TIMER3_4_MODE_UPDOWN = 0x3};enum __nesc_unnamed4270 { CC2430_T34CTL_DIV = 0x5, CC2430_T34CTL_START = 0x4, CC2430_T34CTL_OVFIM = 0x3, CC2430_T34CTL_WDTIF = 0x3, CC2430_T34CTL_CLR = 0x2, CC2430_T34CTL_MODE = 0x0, CC2430_T34CTL_MODE_MASK = 0x3, CC2430_T34CTL_DIV_MASK = 0xe0};enum cc2430_timer3_4_prescaler_t { CC2430_TIMER3_4_DIV_1 = 0x0 << CC2430_T34CTL_DIV, CC2430_TIMER3_4_DIV_2 = 0x1 << CC2430_T34CTL_DIV, CC2430_TIMER3_4_DIV_4 = 0x2 << CC2430_T34CTL_DIV, CC2430_TIMER3_4_DIV_8 = 0x3 << CC2430_T34CTL_DIV, CC2430_TIMER3_4_DIV_16 = 0x4 << CC2430_T34CTL_DIV, CC2430_TIMER3_4_DIV_32 = 0x5 << CC2430_T34CTL_DIV, CC2430_TIMER3_4_DIV_64 = 0x6 << CC2430_T34CTL_DIV, CC2430_TIMER3_4_DIV_128 = 0x7 << CC2430_T34CTL_DIV};enum __nesc_unnamed4271 { CC2430_WDCTL_CLR = 0x4, CC2430_WDCTL_EN = 0x3, CC2430_WDCTL_MODE = 0x2, CC2430_WDCTL_INT = 0x0, CC2430_WDCTL_INT_MASK = 0x3};enum cc2430_timerWDT_mode_t { CC2430_TIMERWDT_MODE_WDT = 0x0 << CC2430_WDCTL_MODE, CC2430_TIMERWDT_MODE_TIMER = 0x1 << CC2430_WDCTL_MODE};typedef uint8_t TMilli;typedef uint8_t T32khz;typedef uint8_t TMicro;typedef uint16_t mac_addr_t;typedef uint8_t ieee_mac_addr_t[8];enum fcf_stuff { FCF_FT_BEACON = 0x0000, FCF_FT_DATA = 0x0001, FCF_FT_ACK = 0x0002, FCF_FT_MAC_COMMAND = 0x0003, FCF_FT_MASK = 0x0007, FCF_SECENC = 0x0008, FCF_FRAMEPENDING = 0x0010, FCF_ACKREQ = 0x0020,
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