host_boot.asm

The evaluation software will be operational for a limited time only. Please contact your nearest IAR

#include <defBF533.h>

/************************L1 Memory***********************************************************************************************/
#define L1_DataBA	0xFF800000		//L1 Data Bank A
#define L1_DataBB	0xFF900000		//L1 Data Bank B	
#define L1_Code		0xFFA00000		//L1 Code SRAM
#define L1_Scratch_END 0XFFB00FFC	//L1 Scratch SRAM (end)
#define ASYNC_Bank0 0x20000000		//Async Bank 0
/********************************************************************************************************************************/

#define SYSCFG_VALUE 0x30			//To allow operations up to 600MHz.

#define OFFSET_( x ) ((x) & 0x0000FFFF)  
#define UPPER_( x ) (((x) >> 16) & 0x0000FFFF)  
#define LOWER_( x ) ((x) & 0x0000FFFF)  

#define SYSMMR_BASE 0xFFC00000
#define COREMMR_BASE 0xFFE00000

#define PF 15
#define file_size 0x324

.section program;


/************************Code to Stay in Supervisor Mode*************************************************************************/
	r1 = SYSCFG_VALUE;
	SYSCFG = r1;					//To allow operations up to 600MHz.

	P0.H = UPPER_(COREMMR_BASE);	// P0 Points to the beginning of CORE MMR Space
	P0.L = LOWER_(COREMMR_BASE);
	
	P1.H = UPPER_(SYSMMR_BASE);		// P1 Points to the beginning of SYSTEM MMR Space
	P1.L = LOWER_(SYSMMR_BASE);
	
	P2.L = START;
	P2.H = START;
	[P0+OFFSET_(EVT15)] = P2;		//Place the address of start code in IVG15 of EVT
	
	R0 = [P0+OFFSET_(IMASK)];		
	R1.L = OFFSET_(EVT_IVG15);
	[P0+OFFSET_(IMASK)] = R1;		//Set(enable) IVG15
	RAISE 15;						//Invoke IVG15 interrupt
	P2.L = WAIT_HERE;
	P2.H = WAIT_HERE;
	RETI = P2;						//Set Reset Return Address 
	RTI;							//Return from Reset Interrupt
WAIT_HERE:	               			//Wait here till IVG15 interrupt is processed
	JUMP WAIT_HERE;
/********************************************************************************************************************************/

/************************Test BMODE Pins*****************************************************************************************/
START:
	[--SP] = RETI;					//RETI must be pushed to enable interrupts.  Boot code in supervisor mode starts here.


SPI_BOOT:
	P2.L = FIO_DIR & 0xffff;		//Set PF as input for slave handshaking
	P2.H = FIO_DIR >> 16;
	R0 = W[P2](Z);
	BITCLR(R0,PF);
	BITSET(R0,4);					//Set PF4 as output (CS)
	W[P2] = R0;

	R0 = 0x0010(Z);
	W[P1+OFFSET_(FIO_FLAG_S)] = R0;	//set CS high (PF4) initially
	
	P2.L = FIO_MASKA_S & 0xFFFF;	//Enable Interrupts for PFs
	P2.H = FIO_MASKA_S >> 16;
	R0 = W[P2](Z);
	BITSET(R0,PF);
	W[P2] = R0;
	
	P2.H = FIO_POLAR >> 16;			//Set Active High Polarity
	P2.L = FIO_POLAR & 0xFFFF;
	R0 = W[P2](Z);
	BITCLR(R0,PF);
	W[P2] = R0;
	
	P2.H = FIO_EDGE >> 16;			//Set Edge Sensitivity
	P2.L = FIO_EDGE & 0xFFFF;
	R0 = W[P2](Z);
	BITSET(R0,PF);
	W[P2] = R0;
		
	P2.L = SIC_IMASK & 0xFFFF;		//Enable Interrupts on System Level for PFs
	P2.H = SIC_IMASK >> 16;
	R0 = [P2];
	BITSET(R0,19);
	[P2] = R0;


	P2.L = IMASK & 0xFFFF;			//Enable Interrupts on Core Level for PFs
	P2.H = IMASK >> 16;
	R0 = [P2];
	BITSET(R0,12);
	[P2] = R0;
	
	P2.H = 0xFFE0;					//Set PF interrupt address within EVT table
	P2.L = 0x2030;
	R0.H = FLAG_INT;
	R0.L = FLAG_INT;
	[P2] = R0;
	
	P2.H = FIO_INEN >> 16;			//Enable PF
	P2.L = FIO_INEN & 0xFFFF;
	R0 = W[P2](Z);
	BITSET(R0,PF);
	W[P2] = R0;
	
#ifdef _DSP_MODE_
     R1 = 0x0005(Z);					// Smaller Value for faster simulation.
#else
     R1 = 0x0085(Z);
#endif
     W[P1+OFFSET_(SPI_BAUD)] = R1;		//set baud rate register

    R0 = 0x5401;
	W[P1+OFFSET_(SPI_CTL)] = R0;		//enable SPI, nondma tx mode, 8bit

	R0 = 0x0010(Z);
	W[P1+OFFSET_(FIO_FLAG_C)] = R0;		//assert CS low (PF4)
	
	P3.H = loader_file;					//This is our pointer to the LDR file
	P3.L = loader_file;
	P2.H = UPPER_(file_size);			//Set P2 to the LDR file size
	P2.L = LOWER_(file_size);

	LSETUP(Begin, End) LC0 = P2;
Begin:
	R0 = B[P3++](Z) ;
	W[P1+OFFSET_(SPI_TDBR)] = R0;		//send out byte
RD_ST:		
	R0 = W[P1+OFFSET_(SPI_STAT)] (Z);
	CC = BITTST(R0,5);					//test bit 5 (RXS) of SPIST0 register to see if the RX Data Buffer is full, if 0 do test again
	IF !CC JUMP RD_ST;
	R0 = W[P1+OFFSET_(SPI_RDBR)] (Z);	//do read
End: NOP;

	R0 = 0x0010(Z);
	W[P1+OFFSET_(FIO_FLAG_S)] = R0;		//assert CS high (PF4)
	
HERE:	JUMP HERE;

FLAG_INT:								//We will vector here if Slave wants to hold us off
	P2.H = FIO_FLAG_C >> 16;
	P2.L = FIO_FLAG_C & 0xFFFF;
	R0 = 0x8000(Z);
	W[P2] = R0;
		
	P0.H = FIO_EDGE >> 16;				//Set level sensitivity to read flag state (for some reason, edge sensitivity does not let you do this)
	P0.L = FIO_EDGE & 0xFFFF;
	R0 = W[P0](Z);
	BITCLR(R0,PF);
	W[P0] = R0;
	
STAY_HERE:
	R0 = W[P2](Z);						//Read the state of PF
	CC = BITTST(R0,PF);
	IF CC JUMP STAY_HERE;				//If it's high, stay here
	NOP;

	R0 = W[P0](Z);						//If it's low, reset edge sensitivity
	BITSET(R0,PF);
	W[P0] = R0;
	

	RTI;
	
.section L1_data;
.byte loader_file[file_size] = "SPI_Slave_HostFile.ldr";