defbf561_add.h

General EXAMPLE project for initialization code. This file will be executed on the processor prior

/********************************************************************************************
 Additional masks and macro definitions that are missed in 'defBF561.h'
 to allow the programmer to use symbolic names for register-access and bit-manipulation 
********************************************************************************************/

/* ********************* PLL AND RESET MASKS ************************ */
/* PLL_CTL Masks */
#define DF                      0x0001              /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
#define MSEL                    0x7E00              /* Multiplier Select For CCLK/VCO Factors */

/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits) */
#define SET_MSEL(x)             (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */

/* PLL_DIV Masks */
#define SSEL                    0x000F              /* System Select */
#define CSEL                    0x0030              /* Core Select */

/* PLL_DIV Macros */
#define SET_SSEL(x)             ((x)&0xF)           /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */

/* PLL_STAT Macros */
#define VSTAT                   0x0010              /* Voltage Regulator Status: Regulator at programmed voltage */
#define CORE_IDLE               0x0040              /* processor is in the IDLE operating mode */
#define PLL_LOCKED              0x0020              /* PLL_LOCKCNT Has Been Reached */
#define SLEEP                   0x0010              /* processor is in the Sleep operating mode */
#define DEEP_SLEEP              0x0008              /* processor is in the Deep Sleep operating mode */
#define ACTIVE_PLLDISABLED      0x0004              /* Processor In Active Mode With PLL Disabled */
#define FULL_ON                 0x0002              /* Processor In Full On Mode */
#define ACTIVE_PLLENABLED       0x0001              /* Processor In Active Mode With PLL Enabled */

/* VR_CTL Masks */
#define WAKE                    0x0100              /* Enable RTC/Reset Wakeup From Hibernate */
#define SCKELOW                 0x8000              /* Enable Drive CKE Low During Reset */
#define HIBERNATE               0x0000              /* Powerdown/Bypass On-Board Regulation */

#define FREQ                    0x0003              /* Switching Oscillator Frequency For Regulator */
#define FREQ_333                0x0001              /* Switching Frequency Is 333 kHz */
#define FREQ_667                0x0002              /* Switching Frequency Is 667 kHz */
#define FREQ_1000               0x0003              /* Switching Frequency Is 1 MHz */

#define GAIN                    0x000C              /* Voltage Level Gain	*/
#define GAIN_5                  0x0000              /* GAIN = 5 */
#define GAIN_10                 0x0004              /* GAIN = 10 */
#define GAIN_20                 0x0008              /* GAIN = 20 */
#define GAIN_50                 0x000C              /* GAIN = 50 */

#define VLEV                    0x00F0              /* Internal Voltage Level */
#define VLEV_085                0x0060              /* VLEV = 0.85 V (-5% - +10% Accuracy) */
#define VLEV_090                0x0070              /* VLEV = 0.90 V (-5% - +10% Accuracy) */
#define VLEV_095                0x0080              /* VLEV = 0.95 V (-5% - +10% Accuracy) */
#define VLEV_100                0x0090              /* VLEV = 1.00 V (-5% - +10% Accuracy) */
#define VLEV_105                0x00A0              /* VLEV = 1.05 V (-5% - +10% Accuracy) */
#define VLEV_110                0x00B0              /* VLEV = 1.10 V (-5% - +10% Accuracy) */
#define VLEV_115                0x00C0              /* VLEV = 1.15 V (-5% - +10% Accuracy) */
#define VLEV_120                0x00D0              /* VLEV = 1.20 V (-5% - +10% Accuracy) */
#define VLEV_125                0x00E0              /* VLEV = 1.25 V (-5% - +10% Accuracy) */
#define VLEV_130                0x00F0              /* VLEV = 1.30 V (-5% - +10% Accuracy) */

/* SYSCR Masks */
#define BMODE_BYPASS            0x0000              /* Bypass boot ROM, execute from 16-bit external memory */
#define BMODE_FLASH             0x0001              /* Use Boot ROM to load from 8-bit or 16-bit flash */
#define BMODE_SPIHOST           0x0002              /* Boot from SPI0 host (slave mode) */
#define BMODE_SPIMEM            0x0003              /* Boot from serial SPI memory */


/* **********************  SDRAM CONTROLLER MASKS  *************************** */
/* EBIU_SDBCTL Masks */
#define EBSZ                    0x000E              /* SDRAM external bank size */
#define EBCAW                   0x0030              /* SDRAM external bank column address width */

/* EBIU_SDGCTL Masks */
#define CL                      0x0000000C          /* SDRAM CAS latency */
#define PASR_ALL                0x00000000          /* All 4 SDRAM Banks Refreshed In Self-Refresh */
#define PASR                    0x00000030          /* SDRAM partial array self-refresh */
#define TRAS                    0x000003C0          /* SDRAM tRAS in SCLK cycles */
#define TRP                     0x00003800         /* SDRAM tRP in SCLK cycles */
#define TRCD                    0x00030000          /* SDRAM tRCD in SCLK cycles */
#define TWR                     0x00180000          /* SDRAM tWR in SCLK cycles */


/****************************************************************************
 EOF
*****************************************************************************/