defbf532_add.h

General EXAMPLE project for initialization code. This file will be executed on the processor prior

/****************************************************************************************
 Additional masks and macro definitions that are missed in 'defBF533.h'
 to allow the programmer to use symbolic names for register-access and bit-manipulation
****************************************************************************************/

/* ********************* PLL AND RESET MASKS ************************ */
/* PLL_CTL Masks */
#define MSEL                    0x7E00              /* Multiplier Select For CCLK/VCO Factors */

/* PLL_STAT Masks */
#define VSTAT                   0x0010              /* Voltage Regulator Status: Regulator at programmed voltage */
#define CORE_IDLE               0x0040              /* processor is in the IDLE operating mode */
#define SLEEP                   0x0010              /* processor is in the Sleep operating mode */
#define DEEP_SLEEP              0x0008              /* processor is in the Deep Sleep operating mode */

/* VR_CTL Masks */
#define VLEV_125                0x00E0              /* VLEV = 1.25 V (-5% - +10% Accuracy) */
#define VLEV_130                0x00F0              /* VLEV = 1.30 V (-5% - +10% Accuracy) */

/* SYSCR Masks */
#define BMODE_BYPASS            0x0000              /* Bypass boot ROM, execute from 16-bit external memory */
#define BMODE_FLASH             0x0001              /* Use Boot ROM to load from 8-bit or 16-bit flash */
#define BMODE_SPIHOST           0x0002              /* Boot from SPI0 host (slave mode) */
#define BMODE_SPIMEM            0x0003              /* Boot from serial SPI memory */


/* **********************  SDRAM CONTROLLER MASKS  *************************** */
/* EBIU_SDBCTL Masks */
#define EBSZ                    0x000E              /* SDRAM external bank size */
#define EBCAW                   0x0030              /* SDRAM external bank column address width */

/* EBIU_SDGCTL Masks */
#define CL                      0x0000000C          /* SDRAM CAS latency */
#define PASR                    0x00000030          /* SDRAM partial array self-refresh */
#define TRAS                    0x000003C0          /* SDRAM tRAS in SCLK cycles */
#define TRP                     0x00003800          /* SDRAM tRP in SCLK cycles */
#define TRCD                    0x00030000          /* SDRAM tRCD in SCLK cycles */
#define TWR                     0x00180000          /* SDRAM tWR in SCLK cycles */

/****************************************************************************
 EOF
*****************************************************************************/