caideng.tan.rpt

彩灯设计程序

; N/A   ; None         ; 14.600 ns  ; lpm_counter:b_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; y[6] ; clk        ;
; N/A   ; None         ; 14.500 ns  ; lpm_counter:b_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; y[3] ; clk        ;
; N/A   ; None         ; 14.100 ns  ; lpm_counter:b_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; y[0] ; clk        ;
; N/A   ; None         ; 14.100 ns  ; lpm_counter:b_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; y[1] ; clk        ;
; N/A   ; None         ; 14.100 ns  ; lpm_counter:b_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; y[2] ; clk        ;
; N/A   ; None         ; 14.000 ns  ; lpm_counter:b_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; y[2] ; clk        ;
+-------+--------------+------------+---------------------------------------------------------+------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
    Info: Processing started: Wed Mar 18 21:47:19 2009
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off caideng -c caideng
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Timing Analysis found one or more latches implemented as combinational loops
    Warning: Node "y[7]$latch" is a latch
    Warning: Node "y[6]$latch" is a latch
    Warning: Node "y[5]$latch" is a latch
    Warning: Node "y[4]$latch" is a latch
    Warning: Node "y[3]$latch" is a latch
    Warning: Node "y[2]$latch" is a latch
    Warning: Node "y[1]$latch" is a latch
    Warning: Node "y[0]$latch" is a latch
Info: Found combinational loop of 1 nodes
    Info: Node "y[0]$latch"
Info: Found combinational loop of 1 nodes
    Info: Node "y[1]$latch"
Info: Found combinational loop of 1 nodes
    Info: Node "y[2]$latch"
Info: Found combinational loop of 1 nodes
    Info: Node "y[3]$latch"
Info: Found combinational loop of 1 nodes
    Info: Node "y[4]$latch"
Info: Found combinational loop of 1 nodes
    Info: Node "y[5]$latch"
Info: Found combinational loop of 1 nodes
    Info: Node "y[6]$latch"
Info: Found combinational loop of 1 nodes
    Info: Node "y[7]$latch"
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 101.01 MHz between source register "lpm_counter:\x1:a[0]_rtl_1|alt_counter_f10ke:wysi_counter|q[3]" and destination register "lpm_counter:b_rtl_0|alt_counter_f10ke:wysi_counter|q[2]" (period= 9.9 ns)
    Info: + Longest register to register delay is 8.500 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC7_A20; Fanout = 3; REG Node = 'lpm_counter:\x1:a[0]_rtl_1|alt_counter_f10ke:wysi_counter|q[3]'
        Info: 2: + IC(1.300 ns) + CELL(1.500 ns) = 2.800 ns; Loc. = LC8_A22; Fanout = 1; COMB Node = 'LessThan~98'
        Info: 3: + IC(0.200 ns) + CELL(1.400 ns) = 4.400 ns; Loc. = LC7_A22; Fanout = 14; COMB Node = 'LessThan~55'
        Info: 4: + IC(1.400 ns) + CELL(1.400 ns) = 7.200 ns; Loc. = LC5_A19; Fanout = 12; COMB Node = 'LessThan~99'
        Info: 5: + IC(0.200 ns) + CELL(1.100 ns) = 8.500 ns; Loc. = LC3_A19; Fanout = 13; REG Node = 'lpm_counter:b_rtl_0|alt_counter_f10ke:wysi_counter|q[2]'
        Info: Total cell delay = 5.400 ns ( 63.53 % )
        Info: Total interconnect delay = 3.100 ns ( 36.47 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 3.500 ns
            Info: 1: + IC(0.000 ns) + CELL(2.200 ns) = 2.200 ns; Loc. = PIN_79; Fanout = 18; CLK Node = 'clk'
            Info: 2: + IC(1.300 ns) + CELL(0.000 ns) = 3.500 ns; Loc. = LC3_A19; Fanout = 13; REG Node = 'lpm_counter:b_rtl_0|alt_counter_f10ke:wysi_counter|q[2]'
            Info: Total cell delay = 2.200 ns ( 62.86 % )
            Info: Total interconnect delay = 1.300 ns ( 37.14 % )
        Info: - Longest clock path from clock "clk" to source register is 3.500 ns
            Info: 1: + IC(0.000 ns) + CELL(2.200 ns) = 2.200 ns; Loc. = PIN_79; Fanout = 18; CLK Node = 'clk'
            Info: 2: + IC(1.300 ns) + CELL(0.000 ns) = 3.500 ns; Loc. = LC7_A20; Fanout = 3; REG Node = 'lpm_counter:\x1:a[0]_rtl_1|alt_counter_f10ke:wysi_counter|q[3]'
            Info: Total cell delay = 2.200 ns ( 62.86 % )
            Info: Total interconnect delay = 1.300 ns ( 37.14 % )
    Info: + Micro clock to output delay of source is 0.700 ns
    Info: + Micro setup delay of destination is 0.700 ns
Info: tco from clock "clk" to destination pin "y[2]" through register "lpm_counter:b_rtl_0|alt_counter_f10ke:wysi_counter|q[0]" is 18.100 ns
    Info: + Longest clock path from clock "clk" to source register is 3.500 ns
        Info: 1: + IC(0.000 ns) + CELL(2.200 ns) = 2.200 ns; Loc. = PIN_79; Fanout = 18; CLK Node = 'clk'
        Info: 2: + IC(1.300 ns) + CELL(0.000 ns) = 3.500 ns; Loc. = LC1_A19; Fanout = 12; REG Node = 'lpm_counter:b_rtl_0|alt_counter_f10ke:wysi_counter|q[0]'
        Info: Total cell delay = 2.200 ns ( 62.86 % )
        Info: Total interconnect delay = 1.300 ns ( 37.14 % )
    Info: + Micro clock to output delay of source is 0.700 ns
    Info: + Longest register to pin delay is 13.900 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_A19; Fanout = 12; REG Node = 'lpm_counter:b_rtl_0|alt_counter_f10ke:wysi_counter|q[0]'
        Info: 2: + IC(2.700 ns) + CELL(1.500 ns) = 4.200 ns; Loc. = LC3_B14; Fanout = 4; COMB Node = 'reduce_nor~80'
        Info: 3: + IC(0.000 ns) + CELL(3.400 ns) = 7.600 ns; Loc. = LC2_B20; Fanout = 2; COMB LOOP Node = 'y[2]$latch'
            Info: Loc. = LC2_B20; Node "y[2]$latch"
        Info: 4: + IC(1.400 ns) + CELL(4.900 ns) = 13.900 ns; Loc. = PIN_75; Fanout = 0; PIN Node = 'y[2]'
        Info: Total cell delay = 9.800 ns ( 70.50 % )
        Info: Total interconnect delay = 4.100 ns ( 29.50 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 10 warnings
    Info: Processing ended: Wed Mar 18 21:47:21 2009
    Info: Elapsed time: 00:00:02